Intelop delivers their second generation TCP-Offload Engine SoC IP with integrated G-bit Ethernet MAC and AMBA host bus interface SOC-FPGA to a strategic European OEM customer in Network Security systems and Telecom markets
Santa Clara, California – Jan 19, 2009 -- Intelop Corporation, a leading IP developer, customization & engineering services provider, today announced delivery of their second generation TCP offload engine SoC solution with integrated with ARP hardware module, G Bit Ethernet MAC and AMBA host bus interface running at 2 Gbps sustained rates . It implements control plane and data plane processing of TCP/IP in hardware that is at least 20 times faster than TCP/IP software stack. In addition, it provides, as an option, an ability to integrate other interfaces e.g. PCIe x 4. Intelop designed all blocks, integrated them, verified and implemented this SoC in Altera’s Stratix-II FPGA.
“Because of its advanced scalable architecture, it can be customized to implement differentiated features and performance requirements to meet customer’s specifications e.g. Misc. protocols processing module, in addition to TCP/IP, ARP module, customizable number of simultaneous connections, TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of Session Management table, Session Parameters, scalable size of direct store Packet memories, integrated DDR/SSRAM controllers, choice of PHY interface - XGMII or Serial.
This Integrated TOE+GEMAC+AHB silicon IP with customizable features provides enhanced functionality in Layer-2-5 Switches/Routers, IPS/IDS appliances and Network Security appliances, Severs and NICs. Advanced architecture with built in scalability allows customers to target it to many silicon libraries from 0.18 um-0.090 nm ASIC, SOC or FPGA without compromising performance/ functionality.
The IP core can be used in the appliances ranging from high-end Network Intrusion Detection/Prevention, Network Security, Content Protection/Security, Network Switches appliances and Routers to low-cost Layer-2/3 switching/routing equipment, servers and NICs.
“We utilized our expertise in designing highly successful and advanced technology Multi-Giga bit Enterprise-class IDS/IPS, Network Security appliances employing SOCs also designed by intelop in defining the architecture of this TOE engine,” said Kelly Masood. Intelop also integrated many of these IPs with other standard blocks in SOCs and developed necessary software as total turn key solutions as well.
“We are excited about this new crown jewel and the ability to develop value-added networking silicon and total solutions for our customers.” said Kevin Moore of Intelop.
See what intelop can do for you!
Intelop Corporation is a custom IP developer, SoC/ASIC/FPGA integrator and engineering services provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IP and services with comprehensive hardware and software experience.
http://www.intelop.com Intelop Corporation
Ph: 408-496-0333, Fax: 408-496-0444
info@intelop.com
Related Semiconductor IP
- 1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)
- 1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
- 10 G bit TCP Offload Engine + PCIe/DMA SOC IP
- 1G TCP Offload Engine TOE Very Low Latency (TOE)
- 1G TCP Offload Engine TOE +PCIe Very Low Latency (TOE+PCIe)
Related News
- Intelop announces Xilinx FPGA development platform for their TCP-Offload Engine SoC IP
- Intelop announces a new Development platform based on Xilinx V5 FPGA for their TCP-Offload Engine SoC IP for customers to easily develop networking applications
- SoC Secure Boot Hardware Engine IP Core Now Available from CAST
- Mirabilis Design Accelerates SoC Development with New System-Level IP Library for Cadence Tensilica Processors
Latest News
- Matrox Video and intoPIX Expand Interoperable IPMX & ST 2110 Solutions with JPEG XS Innovation at NAB 2025
- HCLTech joins Samsung Advanced Foundry Ecosystem as a Design Solution Partner
- TeraSignal to Showcase Retimer-Less PCIe 6.0 over Optics Featuring Synopsys IP at OFC 2025
- Arteris Opens New Engineering Hub in Poland
- Alphawave IP Response to announcement from Qualcomm