Introducing DDR5/DDR4/LPDDR5 Combo PHY IP Core, Silicon Proven in 12FFC for Next-Gen High performance SoCs is available for immediate licensing

28^th March 2022. – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s DDR5/DDR4/LPDDR5 Combo PHY IP Core in 12FFC process node with matching DDR5 Combo Controller IP Core which are silicon proven with High bandwidth and superfast data rate.

The DDR5/DDR4/LPDDR5 Combo PHY and Controller IP Core is also able to run on DDR4, DDR5, LPDDR5 modes separately. The structured yet simple design allows easy adoption into any design architecture and provides low latency and enables up to 5400MT/s throughput. There is availability of special feature of Programmable output impedance (DS) and Programmable on-die termination (ODT). Compliant with DFI version 5.0 Specification, the DDR5 Combo PHY with matching Controller can support up to 16 AXI ports with data width up to 512 bits.

The DDR5/DDR4/LPDDR5 Combo PHY IP core in 12nm FFC process technology supports varied DDR5/ DDR4/ LPDDR5 with Maximum Controller clock frequency of 675MHz, 400MHz, 600MHz resulting in maximum DRAM data rate of 5400MT/s for DDR5, 3200MT/s for DDR4 and 4800MT/s for LPDDR5 respectively. It Supports four modules for flexible configuration CA/DQ_X16/DQ_X8/ZQ. The 12FFC technology comes with added feature of ZQ calibration and supports 4 ranks by each CA module in different consideration of power consumption with an Operating Voltage of Core power of 0.8V.

The DDR5 Combo Controller IP Core is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 specification. It is compliant with different clock frequency for DDR5, DDR4 and LPDDR5. It also supports PHY internal auto decision and has additional features such as Maximum Power Saving Mode (MPSM), Precharge Command modes, Error Checking, and correction (ECC), reordering of transactions for higher performance and Self-Refresh and Power Down operation. It is able to support up to 64GB device density and X4, X8, X16 device types

These IP Cores functionalities are verified in NC-Verilog simulation software using test bench written in Verilog HDL, which are provided with the IP Core delivery.

The DDR5 Combo PHY IP core along with the DDR5 Combo Controller IP Core have been used in semiconductor industry’s Enterprise computing, storage area networks, Embedded systems, Graphics devices and other Consumer Electronics…

In addition to DDR5 IP Core, T2M ‘s broad silicon Interface IP Core Portfolio includes other USB, HDMI, Display Port, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMCs, Serial ATA and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com