Synplicity adds IP savvy to FPGA synthesis tool

Synplicity adds IP savvy to FPGA synthesis tool
By Michael Santarini, EE Times
November 15, 2000 (4:13 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001115S0075

SAN MATEO, Calif. — Synplicity Inc. has enhanced its Synplify Pro FPGA synthesis tool to better support designers integrating intellectual property (IP) cores into high-density FPGAs.

Key new features included in version 6.1 are mixed-Verilog and VHDL support, timing modeling in Synopsys Inc.'s Stamp format and support for Xilinx Inc.'s Modular Design Flow.

"With this release, we are trying to break down some of the barriers for integrating IP into FPGA designs," said Jeff Garrison, director of FPGA products for Synplicity (Sunnyvale, Calif.). The three new capabilities, he said, "will help greatly to knock down those barriers."

The tool also improves the quality of results for Xilinx Virtex-II devices and Altera Apex20K/E families, Garrison said, while adding new support for devices from Actel, Lattice Semiconductor, Lucent, QuickLogic and Triscend.

Garrison said the new mixed-language sup port will allow designers to mix and match Verilog or VHDL into their designs.

Core communication

Traditionally, a designer would have to manually reimplement a core if it were written in a language different from the primary language of the design. The Synplify Pro software enables communication between the cores, eliminating the need to reimplement the core and allowing individual design team members to work on a design with the language to which they are most accustomed.

Version 6.1 of Synplify Pro also includes support for Synopsys' Stamp modeling format and support for the Xilinx Modular Design Flow. Garrison said that by using Synplify Pro in the Modular Design Flow, design team leaders can define modular boundaries for each team member and generate separate netlists and constraints for each section of the design.

In addition, both Synplify Pro and Synplify include new quality of results improvements for Xilinx Virtex-I I FPGAs, including Dynamic shift-register-lookup (SRL) support, automatic inference of up/down counters and support for simultaneous read and write for BlockRAMs.

Both tools also include support for Altera's Apex20K and Apex20KE family of devices and support for Triscend's A7 and E5 hybrid standard cell/programmable devices; Actel 54SXS and eX families; Lattice SuperFast and SuperWide families; Lucent Orca4 family; and QuickLogic QuickDSP family.

The Synplify 6.1 starts at $9,000 and Synplify Pro 6.1 starts at $19,000.