Synopsys launches more-powerful power-analysis tool

Synopsys launches more-powerful power-analysis tool
By Richard Goering , EE Times
May 22, 2000 (6:02 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000522S0065

MOUNTAIN VIEW, Calif. -- Synopsys Inc. this week will launch PrimePower, a full-chip, dynamic power analysis tool that works at the gate level. The offering replaces Design Power, which is still used within Synopsys' Power Compiler synthesis tool but is not sold as a stand-alone device.

PrimePower has advantages over Design Power, said William Ruby, director of marketing for mixed-signal and low-power design at Synopsys. One is the tool's ability to handle designs withpotential capacities of up to 10 million instances. Another is PrimePower's time-based analysis, which lets users view power dissipation as a function of time within a waveform display.

PrimePower models pattern-dependent, capacitive switching, short-circuit and static power consumption, considering instance-specific cell-state dependencies, glitches, multiple loads and nonlinear ramp effects.

To use PrimePower, an engineer first runs an HDL simulator and generates what Synop sys calls a PrimePower interface format (PIF) file. That contains switching activity and hierarchy information. The file is created by programming-language interface routines provided with the tool. PIF files can be generated by Synopsys' VCS Verilog, Cadence's Verilog-XL and NC-Verilog and Model Technology's ModelSim VHDL simulators.

PrimePower also requires ASIC libraries characterized for power in Synopsys' ".db" format, which is accomplished with, but does not necessarily require, Synopsys' PowerArc tool. "PrimePower accuracy is a function of the library information," said Ruby. "If a library is well-characterized, you will typically see very good results."

A third source of input is parasitic back-annotation data, which can be a capacitance table or a detailed standard parasitic format file generated by Synopsys' Arcadia product.

The largest design Synopsys has done had 1 million instances and ran in about four hours on a 2-gigabyte workstation, Ruby said.

Users must run a gate-leve l Verilog or VHDL simulation first to generate PIF files. To limit the impact on the gate-level simulator's run-time, the PIF generation is restricted to design connectivity and time-based transitions. As for accuracy, Ruby said PrimePower results are typically within 10% of Spice or Synopsys' PowerMill -- if the library is properly characterized.

PrimePower outputs text reports, giving a breakdown of power dissipation, and graphical reports that can include histograms and waveforms.

PrimePower goes into production release in September, priced at $78,000 on Unix workstations.