Sofics releases Analog I/O's and ESD clamps for TSMC N5 process
First customer received Sofics ESD protection for high-speed SerDes and fail-safe I/O in TSMC N5
Belgium, August 24, 2020 – Sofics bvba, a leading semiconductor integrated circuit IP provider announced that its TakeCharge® Electrostatic Discharge (ESD) portfolio is silicon proven on TSMC’s advanced 5nm process technology. More than 100 fabless companies use Sofics solutions to enable higher performance, higher robustness while reducing design time and cost of SoC design.
Interface ESD protection in FinFET technology is challenging. FinFET circuits are very sensitive to ESD stress, but the conventional ESD concepts are not effective anymore. “Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology,” said Koen Verhaege, CEO of Sofics.
“SoC designers need custom analog I/O or ESD cells for some applications including high-speed or wireless interfaces, low power or high voltage tolerant pads. However, designing custom ESD cells is quite cumbersome in such advanced technology in terms of the design complexity and challenges.”
“We are proud to report that a leading semiconductor company recently integrated Sofics ESD protection for its high-speed interface and another one for a 1.8V fail-safe I/O.”
Key aspects for the Sofics ESD solutions include ultra-low leakage, small area and low parasitic capacitance. The IP can be used to protect the most sensitive core interfaces against Electrostatic Discharge.
TakeCharge cells as well as robust I/O solutions are readily available from Sofics. One can find more information about FinFET ESD and Analog I/O solutions from Sofics on the Website .
About Sofics
Sofics stands for “Solutions for ICs.” Sofics is an IP provider with a track record in on-chip robustness for ESD, EOS and EMC with an extensive patent portfolio, proven on more than 50 processes. Our 100 licensees have integrated Sofics IP into their IC products. Thanks to close cooperation with some of the leading semiconductor companies, more than 4500 mass-produced ICs are protected by Sofics ESD solutions.
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- Certus Semiconductor adopts AI-powered Solido to accelerate IO library, analog IP and ESD development
- Sofics, ICsense Merge ESD and I/O Technologies, Deliver 3.3V Signalling on Icera's 40nm, 1.8V I/O Baseband Chip
- Sofics Releases Analog IO's and ESD protection clamps for Advanced Applications using TSMC 7nm FinFET process
- Sofics Analog I/O's and ESD clamps proven for TSMC 16nm, 12nm and 7nm FinFET processes
Latest News
- Nuclei Announces Strategic Global Expansion to Accelerate RISC-V Adoption in 2026
- Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems
- Andes Technology Launches RISC-V Now! — A Global Conference Series Focused on Commercial, Production-Scale RISC-V
- Rambus Reports Fourth Quarter and Fiscal Year 2025 Financial Results
- IntoPIX And Cobalt Digital Enable Scalable, Low-Latency IPMX Video With JPEG XS TDC At ISE 2026