SoC collaboration network signs agreement with CSIP
(08/26/2005 1:34 PM EDT)
SAN FRANCISCO — Design and Reuse (D&R), a global collaboration network for sharing system-on-chip (SoC) design resources, said Friday that it has formed a partnership with China Software and Integrated Circuit Platform (CSIP).
The agreement includes a secure entry portal from CSIP to D&R. The agreement also includes a cooperation plan for completing a database, enhancing provider visibility, organizing common events and training.
"I am delighted to see that intellectual property in electronic design contributes to create a connected world," said Gabriele Saucier chair of D&R, in a statement. "We hope to open more market opportunities to D&R partner companies and enlarge the community of 37,000 registered users of our portal."
Yanhui Wang, general manager of CSIP's IC business division, said the agreement with D&R would contribute to establishing appropriate links between CSIP and mature SoC players.
CSIP is an institution through which the Chinese government guides the development of the software and IC industries and provides resources and technical services for innovation.
D&R is partly owned by CMP Media LLC, which also owns EE Times.
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved.
| Your California Privacy Rights | Terms of Service
Related Semiconductor IP
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
- AXI-S Protocol Layer for UCIe
- HBM4E Controller IP
- 14-bit 12.5MSPS SAR ADC - Tower 65nm
Related News
- Synopsys and Arm Strengthen Collaboration for Faster Bring-Up of Next-Generation Mobile SoC Designs on the Most Advanced Nodes
- Sunplus and Ceva Expand Collaboration to Bring Bluetooth Audio to the airlyra SoC Family for Wireless Speakers, Soundbars and other Wireless Audio Devices
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
- aiMotive Signs License Agreement with Socionext for aiWare NPU IP to Power Next-Gen ADAS SoC
Latest News
- The path to RISC-V growth: Why software consistency is becoming crucial
- OpenGMSL™ Association Releases Specification v3.0, Enabling Interoperable GMSL2/3 Ecosystem
- CAST Demonstrates IP Cores for Leading-Edge Technologies at Embedded World 2026
- Global Semiconductor Sales Increase 3.7% Month-to-Month in January
- OpenTitan Ships in Chromebooks: First Production Deployment