Praesum Communications Introduces Serial RapidIO 2.1 Endpoint IP
Silicon-proven Solution Enables RapidIO Connectivity for Military Aerospace and Other Signal Processing Markets
Petaluma, CA -- January 13, 2011 -- Praesum Communications announces general availability of its Serial RapidIO 2.1 Endpoint Core. âOur early access customers have been deploying the 2.1 core for more than a year,â said Praesum CEO Kent Dahlgren. âWe are now offering the core to all customers.â Like the entire Praesum IP product line, the Serial RapidIO 2.1 Endpoint Core provides the following benefits:
Maturity: For more than a decade, Praesum has been delivering and deploying RapidIO technology. We introduced the first RapidIO IP core in 2000, and the first RapidIO switching IP in 2004. With the introduction of the first RapidIO 2.1 Endpoint Core in January 2010, Praesum has the only silicon-proven core that supports FPGA platforms.
Portability: Praesumâs RapidIO 2.1 Endpoint IP is the only RapidIO IP that has been ported to all of the major FPGA and ASIC platforms. This means that your RapidIO-based designs can be easily retargeted to the best FPGA or ASIC platform for the task at hand. This preserves your design investment and shortens your time to market.
Flexibility: Praesum's IP cores are designed to let you include only the functions needed for your application. This saves precious device resources on programmable platforms, which in turn reduces power and cost.
Specific technical benefits of the Praesum RapidIO 2.1 Endpoint IP include:
- Complete implementation of Rev. 2.1 of the RapidIO Physical Layer LP-Serial protocol.
- Implements RapidIO Error Management Extensions
- Supports 1x, 2x, and 4x link widths.
- Management Entity with integrated decoder for RapidIO maintenance transactions.
- Management Entity supports optional soft packet interface which enables software implementations of logical layer functions.
Praesumâs Serial RapidIO 2x Endpoint IP Core is available in two forms: As Verilog RTL source code or as compiled netlists for Xilinx, Altera and Lattice FPGAs. Netlists for Lattice FPGAs are available directly from Lattice Semiconductor.
About Praesum
Praesum Communications is the RapidIO solutions leader. Our Serial RapidIO Endpoint and Switching IP enable next generation systems. Founded in January 2000, Praesum has its headquarters in Petaluma, CA. For more information, visit the Praesum web site at www.praesum.com .
Related Semiconductor IP
- Serial RapidIO IP Core
- Serial RapidIO Controller
- Serial RapidIO LogiCORE IP
- Serial RapidIO - Physical Layer Interface
- Serial RapidIO 2.1 Endpoint IP Core
Related News
- Altera Delivers Industry's First Serial RapidIO 2.1 IP Solution
- Lattice Announces First Low Cost FPGA With Serial RapidIO 2.1 Support
- Lattice Announces Serial RapidIO 2.1 AMC Evaluation Platform
- Praesum Communications Introduces Serial RapidIO Endpoint Core for AMBA 4 AXI4
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack