HDL Design House Webinar: Reducing Integration and Verification Effort in SoC Design
HDL Design House invites you to join the free January 29th, 2019 webinar on optimizing SoC development challenges and achieving reduced time-to-market and built-in security.
Belgrade, Serbia – January 15th, 2019 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a webinar with Arm on SoC design and verification best practices for accelerated time-to-market on January, 29th, 2019. The webinar will be presented by Mike Eftimakis, senior IoT product manager, Arm and Vojislav Krvavac, digital design engineer, HDL Design House.
With increased complexity of designing secure SoC, along with growing challenges in integration and verification stages, managing SoC design efficiently has become a crucial component for successful tape-out. The latest trends and developments in the semiconductor industry demand advanced and integrated solutions to meet aggressive schedules without compromising quality.
The webinar will address the above requirements, providing the attendees answers on how to reduce design and integration effort, lower design risk and accelerate time-to-market. The webinar presenters will also illustrate real life example of overcoming challenges and achieving customer requirements quickly and efficiently. Finally, the reasons why security should be a cornerstone of SoC design and how to reduce time-to-security will be given.
This online event is intended for engineering directors, design and verification managers and engineers needing to optimize SoC development activities for schedule, budgets and technical excellence.
The webinar is taking place on Tuesday, January 29th, 2019, at 9am and 5pm GMT and is free to attend. Joining instructions are available on the webinar registration page.
About HDL Design House:
HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in various architectures and numerous areas of SoC and complex FPGA designs. The company also develops IP cores, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 170 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2015 and ISO/IEC 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). HDL DH joined the Arm® Approved Design Partner program, through which leading SoC design houses are recognized by Arm as accredited partners in specific technologies and activities. For more information, please visit www.hdl-dh.com.
Related Semiconductor IP
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
Related News
- Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
- 2025 TSMC OIP Ecosystem Forum Highlights Aion Silicon’s Leadership in Advanced SoC Design
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development
- Digital Blocks DB9000 Display Controller IP Core Family Extends Leadership in 8K, Automotive, Medical, Aerospace, and Industrial SoC Designs
Latest News
- Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
- A new CEO, a cleared deck: Is Imagination finally ready for a deal?
- SkyeChip’s UCIe 3.0 Advanced Package PHY IP for SF4X Listed on Samsung Foundry CONNECT
- Victor Peng Joins Rambus Board of Directors
- Arteris Announces Financial Results for the Fourth Quarter and Full Year 2025 and Estimated First Quarter and Full Year 2026 Guidance
