Rambus Partners with Samsung to Develop 56G SerDes PHY on 10nm LPP Process
Solution brings scalable ADC-based architecture quickly to networking market, supporting transition to 400GbE Ethernet
SUNNYVALE, Calif. – April 20, 2017 – Rambus Inc. (NASDAQ:RMBS) today announced that it is partnering with Samsung Electronics for its recently launched 56G SerDes PHY to be developed on Samsung’s 10nm LPP (Low-Power Plus) process technology.
The industry-leading 56G SerDes PHY delivers enterprise-class performance across the challenging signaling environments typical of high-speed communication systems and provides PAM-4 and NRZ signaling with a scalable ADC-based (analog-to-digital converter) architecture. This new, flexible architecture addresses the long-reach backplane requirements for the industry transition to 400 GB Ethernet applications.
“There is a demand for increased bandwidth and higher performance systems with the rise of data across enterprise applications,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “Our partnership with Samsung enables us to bring more solutions quickly to market that address the process, power and performance challenges of today’s complex data centers. We are pleased Samsung has selected to work with us, following our successful partnership of the 28G SerDes PHY on their 14nm LPP process technology.”
“Network application is one of our key segments of focus and the composition of our 10LPP network solution and the Rambus 56G solution will be the most competitive choice for high-performance and low-power consumption,” said Ryan Lee, vice president of the Foundry Marketing Team at Samsung Electronics. “Rambus has been a long-term strategic partner with Samsung for high-speed SerDes IP, and this 56G SerDes collaboration will pave the way for the explosive data processing requirements to come.”
The Rambus industry-standard interface offerings are high-quality, complete PHY solutions designed with a system-oriented approach to maximize flexibility in today’s most challenging system environments. For additional information, please visit http://www.rambus.com/serdes.
For additional information on Rambus products and solutions, please visit rambus.com.
Related Semiconductor IP
Related News
- Credo Demonstrates Single-Lane 112G and 56G PAM-4 SerDes IP at TSMC OIP Forum
- Credo Demonstrates 112G PAM4 SR, 56G PAM4 LR, and 56G NRZ SerDes Technology at DesignCon
- Rambus Unveils 56G SerDes PHYs on Leading-Edge FinFET Technology
- Credo Demonstrates Single-Lane 112G and 56G PAM4 SerDes IP Solutions at TSMC 2017 OIP Ecosystem Forum
Latest News
- TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs
- Efficient Computer Raises $60 Million to Advance Energy-Efficient General-Purpose Processors for AI
- QuickLogic Announces $13 Million Contract Award for its Strategic Radiation Hardened Program
- Cadence Reports Fourth Quarter and Fiscal Year 2025 Financial Results
- Renesas Develops 3nm TCAM Technology Combining High Memory Density and Low Power, Suitable for Automotive SoCs