Q&A: Denali's Srivastava bridges EDA, IP domains
Richard Goering, EE Times
(12/15/2006 12:43 PM EST)
(12/15/2006 12:43 PM EST)
Sanjay Srivastava, president and CEO of Denali Software Inc., has led the company since its inception over 10 years ago. Denali today provides verification intellectual property (IP) for memories and standard interfaces, design IP for memories, a flash file development system, and the Blueprint electronic system level (ESL) tool for embedded register design. Srivastava answered some questions about Denali, IP, and EDA in the following interview.
- Is Denali an EDA company, and IP company, or some combination of both?
- What embedded software product are you offering?
- You're putting a big push on NAND flash right now. Why is that?
- Third party IP is a challenging business, with lots of problems around integration and verification. How do you approach those issues?
- You're on the board of the EDA Consortium, and there's been a question about whether EDAC should include IP revenues in its EDA market statistics. What do you think?
- Denali is best known for its memory and IP expertise. So how does your Blueprint product, and its System Register Description Language (System RDL), fit into your strategy?
- How large is Denali now?
- Any thoughts about an IPO?
- Denali is well known for having the best party at the Design Automation Conference every year. What are your plans for 2007?
To read the full article, click here
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related News
- Sanjay Srivastava, Former Denali CEO, Joins Proton Digital Systems as Executive Chairman
- QuickLogic Announces Appointment of Andy Jaros as Vice President of IP Sales
- QuickLogic Announces $1.1M eFPGA IP Contract with new Defense Industrial Base Customer
- QuickLogic to Exhibit at GOMACTech 2025, Showcasing the Australis™ eFPGA IP Generator
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale