PLDA And IP-Maker Enable High Performance Storage Devices with Integrated PCIe 3.0 Controller with NVM Express IP Core
May 31, 2013 -- SAN JOSE, Calif. & AIX-EN-PROVENCE, France -- PLDA, the industry leader in PCI Express® and interface IP solutions and IP-Maker today announced a joint solution integrating PLDA’s XpressRICH3 PCIe 3.0 with IP-Maker’s NVM Express (NVMe) IP cores. Cloud computing, video broadcast and high performance computing applications require high bandwith and low latency storage devices such as PCIe SSDs, enabled by the combination of speed and performance provided by PCIe 3.0 and NVMe protocol.
The integration of the robust PLDA XpressRICH3 PCIe 3.0 controller for ASIC and the full hardware optimized NVMe IP core from IP-Maker delivers best-in-class performance, featuring ultra-low latency and very high data transfer rates. This integrated PCIe with NVMe available for both ASIC designs and FPGA prototyping of ASIC designs will help customers accelerate their system level development and validation, and reduce the risk. It also offloads CPU and OS, resulting in a better server power footprint.
“We are pleased to work with IP-Maker to satisfy demand in this innovative market segment. We believe that the integration of PCIe 3.0 into Solid State Drives (SSDs) along with an NVM Express protocol will be the most powerful and efficient solution for performance computing needs,” said Stephane Hauradou, CTO for PLDA.
“Our mutual customers will benefit from a fully validated solution, helping to reduce time-to-market thanks to faster system integration,” said Mickael Guyard, Product Marketing Director, IP-Maker. “The integration of NVMe IP core with the PLDA PCIe 3.0 controller will deliver the outstanding performance required by customers today.”
PLDA XpressRICH3 for ASIC Specification
PLDA PCIe 3.0 (XpressRICH3) is a high performance, highly-configurable PCI Express endpoint, root port, and switch semiconductor IP compliant to the PCI Express rev.3.0 specification. PLDA XpressRICH3 inherits the leading architecture performance and reliability of PLDA's previous generations of PCI Express interface IP and provides advanced features and configurability
IP-Maker NVM Express IP Core
The NVMe IP core, designed by IP-Maker, is a powerful data transfer manager to be integrated in the PCIe SSD Controller between the PCIe communication interface and the Nandflash controller, therefore off-loading the host CPU. It is fully NVM Express 1.0d compliant.
About PLDA
PLDA designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA that aim to accelerate time-to-market for embedded electronic designers. PLDA specializes in high-speed interface protocols and technologies such as PCIe, and Ethernet since 1996. PLDA provides IP cores with a complete set of tools, including FPGA prototyping cards or System-on-Module components, drivers and APIs and testbenches. These products benefit from a global support and sales organization able to sustain over 2,000 ASIC and FPGA customers worldwide. PLDA is a global company with offices in North America (San Jose, California) and in Europe (France, Italy, Bulgaria). For more information, please visit www.plda.com.
About IP-Maker
IP-Maker is a leader in NVM Express technology and is a contributor to the specification. The full hardware IP-Maker IP cores are available for both ASIC and FPGA designs. Using pre-validated IP cores allows to greatly reducing time-to-market for embedded systems. Multiple evaluation packages are available and come with documentation, encrypted RTL code, simulation model and test bench. IP-Maker also provides services for customized products.
About the NVM Express specification
NVM Express is an optimized, high performance, scalable host controller interface with a streamlined register interface and command set designed for Enterprise and Client systems that use PCI Express* SSDs. NVM Express was developed to reduce latency and provide faster performance with support for security and end-to-end data protection. Defined by 80+ NVM Express Work Group members, the specification, published in March, 2011, provides a flexible architecture for Enterprise and Client platforms.
Related Semiconductor IP
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
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- PLDA and M31 Announce a Compliant PCI Express 3.0 Solution Including PLDA's XpressRICH3 Controller and M31's PHY IP for the TSMC 28HPC+ Process Node at 8 GT/s
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- PLDA Announces Integration of their PCIe 3.0 Controller IP into Kazan Networks' NVMe Over Fabric Fuji ASIC, Providing a Dramatic Increase in Scalability and Flexibility for Storage Applications
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