Philips streamlines SoC for entry-level set-tops

Philips streamlines SoC for entry-level set-tops
By Junko Yoshida, EE Times
December 5, 2000 (12:11 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001205S0035

LOS ANGELES — Philips Semiconductors showed a set-top system-on-chip device at the Western Show last week that streamlines an earlier SoC to target entry-level to midrange set-top boxes. Philips also launched two single-chip channel receivers at the show.

The pnx8320 set-top chip, part of the Nexperia Home Entertainment line, is based on a 32-bit MIPS Technologies core. It is limited to 2-D graphics processing; handles such basic multimedia formats as MPEG-2, Dolby Digital and MP3; and supports one standard-definition stream. By contrast, its predecessor, the pnx8500, packs both MIPS and TriMedia engines to enable support for one high-definition or two standard-definition streams; 3-D as well as 2-D graphics; and such multimedia formats as MP3, AAC and MPEG-4.

But the new chip will "lower system costs while meeting hot specifications," said David Barringer, director of marketing at Philips Se miconductors (Sunnyvale, Calif.). Those include "time-shift recording, Internet access via V.90 software modem for the back channel, and hybrid set-tops that decode both analog and digital transport streams."

Philips sought to minimize costs with the pnx8320 by levering the same intellectual property blocks and software it had used for the pnx8500. To lower the overall set-top system cost, the pnx8230 has an advanced 32-bit unified memory architecture and offers early support for Micron Technology Inc.'s SyncFlash. That new memory architecture lets system OEMs execute code directly from a non-volatile device residing on the main SDRAM memory bus, thus eliminating the need for redundant memory components and simplifying system design.

An on-chip bus running at up to 532 Mbytes/second supports the chip's 133-MHz MIPS 3940 RISC core. The SoC integrates an MPEG system processor, audio DSP, MPEG-2 MP@ML decoder and 2-D graphics engine. On-chip peripherals include USB and PCI, an IDE disk interface and a digital video encoder with six digital-to-analog converters.

The device is sampling and is slated for volume production in the second quarter of 2001. It is priced at $20 each in quantities of 500,000 units.

Front-end receivers

Two new front-end chips are the TDA10045 DVB-T channel receiver, for terrestrial digital video broadcast, and the TDA10021 DVB-C channel receiver, for cable. Both are optimized for the Nexperia engine and are said to support demodulation as well as forward error correction.

The TDA10021 DVB-C, supporting demodulation via 4 to 256 QAM (quadrature amplitude modulation), is optimized for obtaining first intermediate frequencies implementation to minimize component counts.

The TDA10045 DVB-T channel receiver, supporting 2K and 8K demodulation, is capable of channel scanning at less than 20 seconds, according to Jean-Marc Guyot, international product marketing manager of Philips' channel products. Fast scanning capability is important for consumers, but i t becomes particularly crucial "when terrestrial digital TV broadcast is to be received in a mobile environment," Guyot said.

An Oak DSP embedded in the TDA10045 manages synchronization and control of the demodulation process. "We are taking advantage of the flexibility of the DSP" at a time when DVB-T demodulation continues to require tweaking of algorithms, Guyot said.

The TDA10021 and TDA10045 are available now for $8 and $12.50, respectively, in quantities of 100,000 units.