OVP Simulator Smashes SystemC TLM-2.0 Performance Barrier

Releases Imperas-Developed CPU Models With Leading Performance

Thame, U.K. -- February 13, 2009 -- Open Virtual Platforms (OVP) today released new native SystemC transaction level modeling (TLM)-2.0 technology to use with OVP CPU models that run to the speed of one billion (1B) instructions per second (1,000 MIPS).

These models, developed by Imperas, are free to download and use, and are available through the www.OVPworld.org site.

“These are the fastest CPU models available and we are now making them available for free to the SystemC community to work with native TLM-2.0,” says Simon Davidmann, OVP founder and chief executive officer (CEO) of Imperas.

The ability to model CPUs at the Instruction Accurate level for use in virtual platforms as a Virtualized Software Development environment is a key technology made publicly available through OVP.  Now available for SystemC platforms, the OVP CPU modeling capability is complimentary to SystemC’s TLM-2.0 platform technology.

All OVP CPU models now work with TLM-2.0 and include ARM, OpenCores OR1K, MIPS Technologies’ MIPS32® 4K®, 24K® and 34K® core families and the ARC 600 and 700 families.  Models and example bare metal platforms are available as open source from the OVP website, along with examples of each model being used in a SystemC TLM-2.0 platform.

John Aynsley of Doulos has been active in the SystemC community.  “Part of the OSCI TLM-2.0 value proposition is that it makes the development of fast virtual platforms for software development easier to achieve. The alignment of OVP with the TLM-2.0 standard helps address one of the critical requirements for the successful deployment of virtual platforms, which is the ready availability of processor models."

Since OVP was started in March 2008, there have been close to 10,000 downloads of the software and viewings of demonstration videos and presentations.  More than 500 copies of the simulator itself have been downloaded, confirming that design teams are interested in fast, free and easy-to-use virtual platforms.

Previously, OVP processor models had been available for use in OVP-based virtual platforms only.  This release of OVP tools includes the OVPsim simulator and a native OSCI TLM-2.0 interface.  OVP processor models in a SystemC TLM-2.0 simulation run benchmarks such as “Peakspeed” at 500-1,000 million instructions per second.  

"MIPS customers have been asking for TLM-2.0 compatible models of the MIPS cores," remarks Mark Throndson, director of marketing for MIPS Technologies.  "It's great that Imperas is now providing these models through OVP."  

Notes Dave Von Bank, CEO of Posedge Software:  “That OVP has fast models is important, but making them work in SystemC platforms with TLM2.0 is essential.  It is fantastic that Imperas has made its industry-leading performing models now work with the new OSCI SystemC TLM-2.0 standard.”  

“Imperas has responded quickly to the requests of the SystemC community to make available its models in this new industry standard,” affirms Lauro Rizzatti, general manger of EVE-USA.  “TLM-2.0 provides a new level of performance and interoperability for SystemC users.”  

Imperas’ Davidmann has long been an outspoken critic of SystemC TLM’s lack of interoperability.  “With TLM-2.0, OSCI has made significant strides in interoperability, enabling models from different vendors to work together in a virtual platform.  In addition, features such as the Direct Memory Interface (DMI) have increased performance many times over, making TLM-2.0 a viable option for software virtual platforms.”  

Open Virtual Platforms

The goal of OVP is to provide the infrastructure technology –– open source and free, focused on multicore and speed –– for embedded software development, and the infrastructure through the OVPworld.org website for this community to grow.  The technology helps to address problems embedded software developers have when modeling the system on chip (SoC) that hosts their software.  The OVP website (www.OVPworld.org) serves as the portal, with details about the technology, a discussion forum for the community, and links to download each component.  

About Imperas

By blending hardware development, software programming technologies and design processes together, Imperas provides methodologies, technologies and products to enable the efficient programming, debug, and verification of Multiprocessor Systems-on-Chip (MP SoCs).  With an engineering base in the UK, Imperas distributes its products to customers worldwide.  For more information, visit www.imperas.com.  

About OVP

Open Virtual Platforms (OVP) was initiated with the donation by Imperas of approximately $4 million of simulation infrastructure that enables chip designers and software developers to model platforms, systems on chips (SoCs), and multiprocessor SoCs (MP SoCs).  The OVP technology is available for free from www.OVPworld.org and has the support of electronic design automation (EDA) companies, end users and silicon intellectual property (IP) providers.  For more details, visit www.OVPworld.org.