New Reference Designs Enhance Embedded Function Block Of Lattice MachXO2 PLD Family

MachXO2's Unique I2C, SPI and Flash Memory Hard IP also Implemented in New Re-Usable Demonstration Designs

HILLSBORO, OR – JUNE 4, 2012 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of four new reference designs for the low cost, low power MachXO2™ family of programmable logic devices (PLDs). The new reference designs simplify and enhance the usability of the built-in I2C, SPI and User Flash Memory functions in the MachXO2 device's unique Embedded Function Block (EFB). Five new demonstration designs and three updated application notes focused on the embedded, Flash memory-based EFB are also now available.

Since the MachXO2 family's production release, hundreds of customers have utilized the EFB's built-in I2C, SPI and User Flash Memory functions to interface with microprocessors, microcontrollers, memories and other system peripherals in applications such as I/O expansion and bridging, data storage, configuration and power sequencing. Now, the new reference designs extend EFB ease-of-use with ready-to-use RTL code for the following functions, each with standard data and command interfaces:

• I2C-Slave (Lattice reference design number RD1124)
• SPI-Slave (RD1125)
• UFM access (RD1126)
• Embedded Programming (RD1129)

The RTL code is fully commented and parameterized, so it can be easily edited for customized implementations.

The five new demonstration designs implement the EFB reference designs on Lattice low cost hardware development kits, including the discounted MachXO2 Pico Development Kit, in the following system configurations:

• I2C Master with I2C Slave (Lattice demonstration design number UG55)
• SPI Master with SPI Slave (UG56)
• Master I2C & SPI Using 'C' and the LatticeMico8™ Microcontroller (UG54)
• Programming via the Wishbone Bus Interface (UG57)
• Embedded Programming via I2C (UG58)

These designs, each with commented, pre-verified RTL and C code, are easily re-usable to help engineers get a head start on their own implementations. Updated documentation for MachXO2 programming, configuration and EFB hard IP functions can be found in the following application notes:

• TN1204 — MachXO2 Programming and Configuration Usage Guide
• TN1205 — Using User Flash Memory and Hardened Control Functions in MachXO2 Devices User's Guide
• TN1246 — Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide

Pricing and Availability

Lattice's entire portfolio of reference designs optimized for the MachXO2 family can be downloaded at no cost from the Lattice website at www.latticesemi.com/ip.

Promotional pricing for the MachXO2 Pico Development Kit is $29 for kits ordered via the Lattice online store at www.latticesemi.com/store and through Lattice distributors through December 31, 2012, or while promotional quantities last. More information regarding the MachXO2 Pico Development Kit is available at www.latticesemi.com/mxo2-pico-kit.

Demonstration designs, application notes and other information about the Lattice MachXO2 PLD family are located at www.latticesemi.com/machxo2.

All MachXO2 PLDs are fully production qualified and have been shipping since 2011. MachXO2 PLDs feature a broad range of densities, packages and speed grade options and are available for ordering via the Lattice online store and through www.latticesemi.com/sales. Free Lattice Diamond® design software can be downloaded at www.latticesemi.com/latticediamond/downloads.

About Lattice Semiconductor

Lattice is a service-driven developer of innovative low cost, low power programmable design solutions. For more information about how our FPGA, CPLD, and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.