New Architectures Bringing AI to the Edge
By Dylan McGrath, EETimes
October 31, 2018
SAN FRANCISCO — As artificial intelligence (AI) capability moves from the cloud to edge, it is inevitable that chipmakers will find ways to implement AI functions like neural-network processing and voice recognition in smaller, more efficient, and cost-effective devices.
The big, expensive AI accelerators that perform tasks back in the data center aren’t going to cut it for edge node devices. Battle lines are being drawn among various devices — including CPUs, GPUs, FPGAs, DSPs, and even microcontrollers — to implement AI at the edge with the required footprint, price point, and power efficiency for given applications.
To that end, a pair of intriguing architectures created specifically for implementing AI at the edge are being introduced at the Linley Processor Conference on Tuesday by Cadence Design Systems and Flex Logix Technologies. Both focus on bringing AI functionality into edge node devices with an emphasis on reducing the memory footprint.
To read the full article, click here
Related Semiconductor IP
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
Related News
- MIPS S8200 Delivers Software-First RISC-V NPU To Enable Physical AI at the Autonomous Edge
- MIPS and INOVA Collaborate to put Physical AI into the palm of Robotic hands with new Reference Platform
- BrainChip Unveils Radar Reference Platform to Bridge the ‘Identification Gap’ in Edge AI
- SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center
Latest News
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware
- ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025