Modules add Mips to Infineon Carmel DSP core

Modules add Mips to Infineon Carmel DSP core
By Stephan Ohr, EE Times
March 29, 2000 (5:36 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000329S0045

SAN JOSE, Calif. — Infineon Technologies has added extensions to its customizable long-instruction-word (CLIW) Carmel digital signal processor core. In addition to a user-customizable instruction word architecture, the 20XX second-generation Carmel core features PowerPlugs — add-on accelerators that enhance its computational abilities. System-on-chip developers can use that plug-and-play capability to create application-specific computational abilities, according to Infineon.

Applications such as 3G cellular handsets may require many more Mips than a DSP core can deliver, said Shaul Berger, vice president of marketing for DSP cores at Infineon. And many "new" Mips are not traditional, "MAC-type" Mips, Berger said.

Video apps, for example, will benefit from an MPEG-4 PowerPlug. Graphics will benefit from a quad 8-bit arithmetic logic unit's PowerPlug that can process 16 pixels per cycle. And for raw ma th-processing ability, a 2-MAC PowerPlug can be strapped onto the Carmel 20XX core, enabling four multiply-accumulate operations per clock cycle.

In operation, PowerPlug accelerator registers are mapped in the Carmel I/O and respond to 16-bit-wide op codes embedded in the CLIW word. Those are passed to a PowerPlug accelerator along with the operands.

CLIW instructions can control up to four PowerPlug accelerators. For each instruction, the 20XX core provides the memory addresses, controls and wait states. It generates the accelerator op code, provides the operands for any math operation from memory and writes the results back to memory. The accelerator decodes its own instruction set, controls its own registers and implements the desired data path. The PowerPlug modules are tightly coupled to Carmel's DSP core and are viewed by the software as built-in execution units of the DSP data path.

The 20XX core's instruction set is a superset of the first-generation Carmel DSP 10XX core. The 20XX softwar e tools will recognize the customizable instructions intended for PowerPlug modules.

Infineon said that adding PowerPlug modules can effectively double Mips performance with a penalty in power dissipation. In its first release, the 20XX core will run at up to 300 MHz. The 20XX core will be available in the fourth quarter.

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