Magma Introduces Titan -- First Platform to Combine Full-Chip, Mixed-Signal, Analysis and Verification for IC Design
Unequaled integration and automation of simulation, analog optimization, chip finishing and physical verification
SAN JOSE, Calif. -- Feb. 27, 2008 – Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today announced Titan™, the first full-chip mixed-signal design, analysis and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.
Because Titan is based on Magma’s unified data model, it works seamlessly with Magma’s Talus® digital IC implementation, FineSim™ circuit simulation, QuickCap® TLx transistor-level extraction (also announced today) and Quartz DRC and Quartz LVS physical verification products. As a result, analog and digital design teams are no longer isolated and can have clear visibility into their counterparts’ design space.
“Today’s announcement marks another significant milestone in Magma’s history of delivering game-changing advances in IC design,” said Rajeev Madhavan, Magma chairman and chief executive officer. “With Talus for digital design and Titan for mixed signal, we have achieved a level of integration that the electronic design automation industry has never before provided chip designers.”
“Analog/mixed-signal design tools have not kept up with Moore’s Law the same way digital design tools have,” said Suk Lee, general manager of Magma’s Custom Design Business Unit. “With its unequaled automation of analog IP optimization and process migration, unified simulation, physical verification, physical design and chip finishing environment – and live integration with the digital design flow – Titan is a quantum leap in the evolution of mixed-signal design.”
Titan: An Evolution in Analog/Mixed-Signal Design
Today, analog design flows and teams are isolated from the digital world. Analog integrated circuits are still largely full-custom and are painstakingly crafted by hand. In addition to being time-consuming and prone to error, this transistor-level design style does not allow an existing design to be easily transferred to a new foundry or process/technology node. Instead, the migration of such a design effectively requires the circuit to be re-implemented from the ground up. With Titan, analog designers will still apply their expertise in defining the first circuit topology, but porting to new nodes will be significantly easier.
Lightning-Fast, Automated Chip Finishing and Live Integration with Digital Implementation
In traditional flows, chip finishing – the point at which the digital and analog blocks of a design are placed and routed together – is a time-consuming and manual task. Titan Chip Finishing, the first product to be released on this platform, provides complete and automated chip finishing capabilities. This fast, high-capacity system integrates mixed-signal layout with the Talus place-and-route capabilities. It can manipulate the largest designs with ease, automates analog and special net routing through an efficient constraints-based approach and makes all mixed-signal layout changes immediately available for physical and timing verification sign-off analysis through a live interface with Talus, Quartz DRC and Quartz LVS. Titan Chip Finishing can implement late engineering change orders (ECOs) that affect both analog and standard-cell components without significantly delaying the schedule.
Highly Efficient Full-Chip Circuit Simulation
Titan offers an integrated simulation environment using the industry’s leading circuit simulator, FineSim, along with the gold standard tool for parasitic extraction, QuickCap TLx. When coupled with ground-breaking schematic driven layout, analog circuit optimization, and analog placement-and-routing, Titan provides a level of efficiency in the analog design domain that is similar to that of the digital domain. For true mixed-signal design, the FineSim interface also allows for full-chip circuit simulation, offering SPICE-level accuracy for the analog portions of the design and fast SPICE-level accuracy for the digital portions of the design. This ensures that the analog/digital interfaces are well simulated and verified before committing the chip to silicon.
Titan Chip Finishing is available now. For more on how Magma integrates analog and digital design to accelerate development of mixed-signal designs, download “The Titan Unified, Automated, Full-Chip Mixed-Signal Design Solution” white paper at www.magma-da.com/WPTitan.html.
About Magma
Magma's software for designing integrated circuits (ICs) is used to create complex, high-performance chips required in cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma's EDA software for IC implementation, analysis, physical verification, circuit simulation and characterization is recognized as embodying the best in semiconductor technology, enabling the world's top chip companies to "Design Ahead of the Curve"™ while reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Siemens' state-of-the-art Symphony Pro platform expands mixed signal IC verification capabilities
- ELECTRA IC Marks a Decade of Design and Verification Excellence at CES 2024
- Siemens introduces Innovator3D IC - a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers