Menta Announces New Software Version and New Adaptive DSP at DAC 2020
The proven eFPGA pioneer introduces a new level in flexibility with Origami Programmer 2020.1 and Menta’s Adaptive DSP solution at DAC 2020
Sophia-Antipolis, France – July 15, 2020 – Menta today announced the release of the new Menta Origami Programmer 2020.1, an enhanced version of the company’s innovative, robust and easy-to-use programming software.
The new Menta Origami Programmer 2020.1 can be demonstrated through webEx and evaluation licenses delivered through the Menta Starter Pack (MSP).
Also announced at Design Automation Conference (DAC) 2020, the virtual experience conference, is Menta’s Adaptive Digital Signal Processor (DSP) solution. The newly introduced Adaptive DSP solution can be inferred automatically using Menta Origami tool suite within the user’s embedded FPGA (eFPGA).
“We are very excited to announce Menta Origami Programmer 2020.1 software and Menta’s DSP solution,” said Managing Director of Menta Yoan Dupret. “Until recently, the only way to provide flexible logic to a system was to add a programmable integrated circuit companion device to an ASIC. eFPGA IPs are a game changer for chip designers in countless industries, including artificial intelligence, aerospace and defense, automotive and security. Our adaptive DSP is pushing this flexibility a step further by allowing the eFPGA IP itself to adapt to chip designers’ specific requirements”
The Adaptive Menta DSP solution will allow users to implement the ideal DSP architecture within the eFPGA IP that better suits the hardware requirement. Operand size can be chosen for both the multiplier and the arithmetic logic unit (ALU).
The DSP block operating modes are programmable through the bitstream. It can dynamically be reconfigurable, and its behavior can be controlled at clock cycle level.
A Menta FIR generator empowers users to generate RTL code of an optimized FIR using Menta patented DSP FIR engine. The range of the FIR supported can be set between 4 and 512 taps, allowing users to define the number of DSP to use within their architecture as well as the data bus, and the ALU size, helping users meet frequency, area and latency goals.
DSP configuration is made easy through Origami Designer eFPGA IP software graphical interface and the adaptive DSP is automatically inferred by Origami Programmer synthesis.
Visitors to DAC 2020, a virtual experience, can learn more about Menta’s technological innovations at www.menta-efpga.com. A whitepaper about DSP is available upon request at: https://dac2020.pathable.co/organizations/5FbETpQuPPHBaRFcR.
About Menta
Menta is a privately held company based in Sophia-Antipolis, France. For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is the proven eFPGA pioneer whose design-adaptive standard cells-based architecture and state-of-the-art tool set provides the highest degree of design customization, best-in-class testability and fastest time-to-volume for SoC design targeting any production node at any foundry. For more information, visit the company website at: www.menta-efpga.com.
Related Semiconductor IP
- eFPGA
- eFPGA on GlobalFoundries GF12LP
- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
- eFPGA Soft IP
- Radiation-Hardened eFPGA
Related News
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
- Redefining Mobile Experiences with AI-Optimized Arm CSS for Client and New Arm Kleidi Software
- Siemens delivers a major leap toward mainstream 3D-IC adoption with new Calibre 3DThermal
Latest News
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects