IP99, Virage Logic sponsor system-chip design contest
IP99, Virage Logic sponsor system-chip design contest
By Michael Santarini, EE Times
January 11, 1999 (2:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990111S0025
Core vendor Virage Logic Inc. (Fremont, Calif.) and IP99 conference organizers have jointly announced the first annual IP99 SOC Design Contest. According to the organizers, entries will be judged on the level of innovation and creative use of intellectual property and memory cores in the development of systems-on-chip. Event organizers have assembled a judging panel of industry experts, including Yervant Zorian, chief technology adviser at Logic Vision Inc.; King Pang, vice president of engineering, consumer products division, LSI Logic Corp.; and Sang Wang, co-founder of Epic Design Technology Inc. and now an independent investor and adviser to electronic design companies. Winners will be announced at IP99 on Tuesday, March 23, at a 6:30 p.m. dinner event and industry panel discussion at the Santa Clara Convention Center. Grand prize will be a free memory IP core from Virage Logic (valued up to $50,000), or a credit for $50 ,000 that can be used toward the purchase of any standard product in the Virage Logic catalog. In addition, each grand-prize design team member, up to a total of six members, will receive a digital camera to recognize individual accomplishment. First-place winning teams in each category will be recognized with a $500 gift certificate toward a celebration party in their home town at the establishment of their choice. Participants may choose among three application categories: consumer, communications or computers; or three technology categories: non-volatile, DRAM or other memory structures. A design does not need to be in production to be considered; however, it must be taped out. To get an application, including all design criteria, contact Nilu Aghel at Virage Logic, (510) 360-8011, e-mail nilu@virlog.com or visit the Virage Logic Web site. All entries must be postmarked no later than Feb. 15.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related News
- Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
- Synopsys Accelerates Chip Design with NVIDIA Grace Blackwell and AI to Speed Electronic Design Automation
- Strategies for Addressing More Complex Custom Chip Design
- Electronic System Design Industry Posts $4.9 Billion in Revenue in Q4 2024, ESD Alliance Reports
Latest News
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms