IP Cores, Inc. Announces a Family of High-Speed AES/LRW IP Cores Supporting IEEE P1619 Standard

Palo Alto, California, July 11, 2006 -- IP Cores, Inc., setting the benchmark for security IP cores, today announced a family of IP cores supporting the secure storage standard IEEE P1619. New LRW2 IP cores enable System on Chip (SoC) vendors to select the smallest LRW core of the family that satisfies the clock / throughput requirements.

"Addition of the high-throughput LRW core to our portfolio enables SoC designers to deliver solutions with a very attractive throughput-to-area ratio at a low core acquisition cost," said Alex Tesler, president of IP Cores. "By choosing LRW2, our customers can precisely tailor the core area to match the throughput needs."

High-speed Encryption Protects Data on a Hard Drive
Advanced Encryption Standard (AES) is used the IEEE standard P1619 for hard disk encryption. Addressing the market demand for high-speed AES crypto solutions for this market, IP Cores’ LRW2 implements the AES/LRW mode. LRW2 is designed for throughput between 25.6 and 128 Mbits per MHz.

LRW2 configurations support AES/LRW encryption throughput up to 70+ Gbps in a single core using 90 nm process, with easy parallelization to reach throughput of 100 Gbps and beyond. Gate count for a fully self-contained LRW2-25.6 starts at 44K gates.

LRW2 family contributes to the IP Cores’ fast-growing portfolio of AES-based security IP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security IP cores. Founded 2 years ago, the company provides IP cores to protect communications, storage and intellectual property.