Intento Design announces the launch of ID-Calibre, an ID-Substrate extension for behavioural TCAD simulation on a complete AMS chip

Paris, July 30, 2020: Intento Design, a rising EDA startup founded in 2015, provides innovative AI-based tools for analog design acceleration. Born from 25 years of research, the company aims to revolutionize traditional analog design methodology, enabling our customers to produce first-time-right AMS chips in a significantly shorter time.

After the launch of ID-Substrate, a reliability tool for early detection and prevention of all substrate parasitics, Intento Design presents ID-Calibre, an AI-based calibration tool (full release before the end of 2020). While ID-Substrate models a substrate of a complete chip as an active 3D physical model in just a few seconds, ID-Calibre calibrates the extracted substrate model for any foundry design kit, melding AI/ML with semiconductor physics. This addition answers the industry need for fast and accurate early failure prediction, critical in automotive/aerospace, as well as power management, medical, and defence applications.

Ramy Iskander, CEO & founder of Intento Design, clarifies how ID-Calibre opens new market opportunities, “ID-Calibre eliminates the need for empirical calibration or test structure fabrication, effectively bringing better market competitiveness and increased ROI to IDMs, fabless, and design houses.”

Iskander adds, “Think of ID-Substrate/ID-Calibre as a behavioural TCAD simulation of a complete AMS chip 1000x faster than traditional TCAD finite element methods”.

The introduction of ID-Calibre will further accelerate accurate prediction of all potential substrate failure areas detected by IDSubstrate, while also eliminating test structure fabrication and foundry measurement expenses.

The images below illustrate how ID-Substrate/ID-Calibre set predicts substrate failures and guides layout adjustment before tape-out and fabrication. A power-on-reset signal is systematically generated when the chip is powered on. ID-Substrate analysis detected the problem area and layout adjustment was performed to protect the POR block from minority carriers induced by the output driver resistor switch. The extraction time was 1.606 seconds for a total of 2016 diodes, 8283 resistors, and 3309 homojunctions.

PowerOnReset Signal Generator: Left – minority carrier propagation detected, Right – correction made by layout adjustment.

All actors of the semiconductor ecosystem, from foundries to design houses, can profit from ID-Substrate/ID-Calibre to immunize their chips against substrate failures, thus boosting their ROI and shortening time-to-market.