Intel Chip Performs 10 Trillion Calculations per Second
April 19, 2018 -- Because of the Intel® Stratix® 10’s unique design, it can whip through calculations at blinding speeds – often 10 to 100 times faster than the chips in consumer devices. Intel Stratix 10 FPGAs – the latest version came out in February – are capable of 10 TFLOPS, or 10 trillion floating point operations per second. The Stratix 10 is the fastest chip of its kind in the world.
FPGAs, or field programmable gate arrays, are a special class of computer chip that is surging in importance with the rise of applications like speech-recognition, artificial intelligence, next-generation wireless networks, advanced search engines and high-performance computing.
Unlike traditional central processing units (CPUs) that power today’s laptops and desktops, FPGAs can be customized – or reprogrammed remotely and on the fly – to perform highly specialized computing tasks.
Related Semiconductor IP
- SATA Host on Altera Arria II GX
- SATA Device Controller on Altera Arria II GX
- Aurora-like 8b/10b @3Gbps for ALTERA Devices
- Aurora-like 64b/66b @14Gbps for ALTERA Devices
- eCPRI Altera® FPGA IP
Related News
- Stratix 10 FPGA: REFLEX CES is Shipping the Cloud Computing COTS Board "XpressGXS10-FH200G", and the Sargon Stratix 10 GX Development Kit
- Exostiv Labs now supports Intel Stratix 10 FPGA
- Stratix 10 SoC: REFLEX CES is releasing to market its new version of the COM Express module based on Stratix 10 SoC technology from Intel PSG
- Stratix 10 FPGA: REFLEX CES launches an 800G acceleration card
Latest News
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development