IBM expands family of high-speed ASIC cores

New offerings target consumer and high speed applications

East Fishkill, NY, February 10, 2004 - IBM today announced the availability of three new custom chip cores designed for consumer, networking and storage customer applications. With these new offerings, IBM is expanding its industry-leading family of ASIC technologies from high-end systems to consumer applications.
As part of today's initiative, IBM has released three new 130 nanometer (nm) High Speed SERDES (HSS) cores for its Cu-11 application specific integrated circuit (ASIC) family. SERDES, which stands for serial-deserializer, is essentially a circuit technique for rapid transmission of large amounts of structured data. The new cores include:

• a 6.4Gbps core for switched backplane upgrades;
• a Fibre Channel Standard core for the newest generation interfaces for storage applications at 4.25 Gbps;
• and a core for next generation I/O interconnect based on the emerging PCI Express standard.

This new set of IBM HSS cores supports more than a dozen high-speed interface standards and a number of emerging technologies — including a fully compliant PCI Express core, which provides the next generation of processor and component interconnect with an array of interoperable industry platforms. IBM HSS cores also offer full compliance with industry standards and are validated using procedures and methodologies specifically required by those standards.

"With today's announcement and new SERDES offerings, IBM is increasing its ASIC core technology and performance leadership," said Tom Reeves, vice president, ASIC product group, IBM Technology Group. "Both the breadth of the offering and the quality of data transmission will help our customers bring new applications to market in a timely and cost-effective manner through proven, integrated, high performance cores."

Initial customers for IBM's new HSS cores are expected to receive ASIC parts in the first quarter of this year. Agilent Technologies is among this group of early customers.

"Agilent's Tachyon product line is the market leader in Fibre Channel controllers and has a very successful history using IBM ASIC with integrated SERDES," said Erik Ottem, director of marketing, I/O Storage Division, Agilent Technologies. "Incorporating IBM 0.13um ASIC and HSS technology into its future Fibre Channel Controllers is key for Agilent to extend its performance leadership in the storage networking segment in 2004."

IBM's HSS cores were developed to provide industry-leading jitter performance and equalization support for enhanced system performance with the lowest possible BER (Bit Error Ratio). The new Fibre Channel HSS core not only supports the latest 4.25Gbps speed currently being drafted by the standards committee, but also provides backwards compatibility to existing Fibre Channel speeds as well as support for common SATA (Serial ATA) and SAS (Storage Attached SCSI) applications. This combination enables storage system flexibility with a single core offering.

With the new 6.4Gbps core, IBM provides a major step forward in the equalization capabilities of integrated SERDES with the introduction of a state-of-the art multi-tap DFE (Decision Feedback Equalizer). This sophisticated equalization technology gives system vendors the capability to upgrade legacy systems to industry leading-capacities. The enhanced capabilities of these new cores, along with their backwards compatibility to previous applications, will enable system vendors to deliver on future-proof strategies developed for their customers.