Intel exec says fabless model "collapsing"
Rick Merritt, EETimes
4/24/2012 1:10 PM EDT
SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
To read the full article, click here
Related Semiconductor IP
- 5G-NTN Modem IP for Satellite User Terminals
- AXI-S Protocol Layer for UCIe
- HBM4E Controller IP
- 14-bit 12.5MSPS SAR ADC - Tower 65nm
- 5G-Advanced Modem IP for Edge and IoT Applications
Related News
- Panelists question fabless model viability
- New semi model: fabless and designless
- Is China's fabless model sustainable?
- Fabless firms outpace IDMs in costs, gross margins
Latest News
- OpenTitan Ships in Chromebooks: First Production Deployment
- Breker Verification Systems Adds RISC‑V Industry Expert Larry Lapides to its Advisory Board
- Weebit Nano’s ReRAM Selected for Korean National Compute-in-Memory Program
- Marvell Extends ZR/ZR+ Leadership with Industry-first 1.6T ZR/ZR+ Pluggable and 2nm Coherent DSPs for Secure AI Scale-across Interconnects
- BrainChip Announces Neuromorphyx as Strategic Customer and Go-to-Market Partner for AKD1500 Neuromorphic Processor