eASIC Appoints ASIC and FPGA Industry Expert Mo Movahed as Vice President of Software Engineering
SANTA CLARA, Calif .-- April 11, 2008
-- eASIC Corporation, a provider of zero mask-charge ASIC devices, today announced it has appointed Mo Movahed as Vice President of Software Engineering. Movahed will spearhead the development of design tools and methodologies for eASIC’s current and next generation silicon products enabling customers to further increase the number of designs per engineer per year. Movahed will report directly to Ronnie Vasishta, eASIC President and CEO.
"Mo brings tremendous knowledge and experience to eASIC at this exciting time of our company’s growth,” said Vasishta. "Our Nextreme family is gaining tremendous market acceptance, and we will continue to simplify the design flow as we aggressively strive to bring affordable silicon customization to the masses. Mo and his team will play a pivotal role in helping eASIC achieve this mission.”
Mo Movahed brings over 24 years of software engineering experience in the ASIC and FPGA industry. Most recently, Mo was Vice President of Engineering at Atrenta, an EDA company, and helped the company to develop and release RTL analysis and verification tools,. Prior to that, Movahed was Vice President of Software Engineering at Lattice Semiconductor, and held senior management positions at Cadence Design Systems and Xerox Corporation.
“I'm thrilled to be part of eASIC and work with such a talented team," said Mo Movahed. “eASIC offers a very unique and innovative solution to address the ASIC market needs. I look forward to helping the company reach its next stage and fully realize its long-term potential.”
Movahed holds a Bachelors degree in computer engineering from the University of California, Los Angeles and a Masters degree in electronic engineering from the University of Southern California where he worked towards his PhD.
About eASIC
eASIC is a fabless semiconductor company offering breakthrough zero mask-charge ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer ASICs with no mask-charges and no minimum order quantity,
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com.
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- CAN-FD Controller
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- eASIC and INNOTECH Form Strategic Partnership for Distribution of Programmable ASIC Products in Japan
- eASIC Selects Fujitsu as Foundry Supplier for 90nm Structured ASIC
- eASIC Names Kaushik Banerjee Vice President of Engineering
- eASIC Expands in Europe by Adding New Channel Partners
Latest News
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development