DSP Group taps Tality as SoC design center
DSP Group taps Tality as SoC design center
By Michael Santarini, EE Times
August 29, 2000 (3:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000829S0064
SAN JOSE, Calif. DSP Group Inc. has approved Tality Corp., the electronic design services spin-off of Cadence Design Systems Inc., as a system-on-chip (SoC) design center for its customers. Under the nonexclusive agreement, Tality will provide design-to-manufacture chips to licensees of DSP Group's SmartCores family, the companies said.. The certification will give Tality greater access to DSP Group's new technology and intellectual property (IP), which Tality will integrate into SoC designs for mutual customers. Tality will also tap DSP Group's SmartCores IP to produce hard cores that comply with the design rules of target foundries. Tality's primary SoC design center, in Livingston, Scotland, created the Aplio Trio, a single-chip processor for Internet telephony that contains two Oak DSP cores from DSP Group.
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related News
- Aion Silicon Expands Barcelona Design Center to Meet Surging Demand for ASIC and SoC Solutions
- ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoC
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
- Imagination GPU Powers Renesas R-Car Gen 5 SoC
Latest News
- SEMIFIVE Pulls Ahead in AI ASIC Market, Expanding Lead with Successive NPU Project Wins
- M31 Reports Record NT$1.78 Billion Revenue in 2025 as Advanced Node Royalties Begin to Emerge
- Silvaco Reports Fourth Quarter and Full-Year 2025 Financial Results
- Klepsydra Technologies and BrainChip Announce Strategic Partnership to Deliver Heterogeneous AI Runtime for Akida™ Neuromorphic Processors
- Alchip Reports ASIC-Leading 2nm Developments