Solving Critical Bugs: Tracing from Power-Up for DesignWare ARC processors
18th July 2017 - LIMERICK, IRELAND -- Imagine a scenario where you have issues debugging your hardware immediately after a reset or power-up. For example, a complex bug occurs immediately after the target hardware is powered-up, and only happens when executing code in real-time from reset.
Using a strategy like setting a breakpoint immediately after reset and then stepping through the code, will not help solve the problem because in this case the breakpoint causes the bug to disappear. Even halting immediately after reset and activating real-time trace will not solve it, because halting the code execution to allow trace activation causes the malfunction to disappear. This bug is difficult to resolve so the engineer needs to use the full power of a debugger to fix it.
The Ashling Ultra-XD trace probe for Synopsys DesignWare ARC HS and EM Processors allows you to solve this kind of debug issue efficiently, by ensuring real time trace is active from the moment the processor is reset or powered on. By having the trace feature activated and collecting trace code and data from power-up or following a reset, engineers can debug complex bugs which occur during this critical phase, in the same way as during all other phases of code execution. In fact, having the ability to record real-time trace from power-up, is essential in many embedded applications, not only for solving bugs but also in safety-critical and performance-critical applications where the developer requires full visibility of all code executed, including the code executing immediately after a reset. This visibility is now available if using Ashling’s Ultra-XD trace probe together with Synopsys DesignWare ARC RTT trace technology.
Hugh O’Keeffe, Engineering Director from Ashling Microsystems, said “Recording real-time trace data from power-up in embedded applications is an important feature in embedded systems debugging. It can be difficult to isolate the source of a problem which occurs immediately after power-up. Ashling’s Ultra-XD trace hardware for Synopsys ARC HS and EM processors provides full debug control and visibility, including within the critical phase from target hardware power-up.”
There are, of course, many other embedded debug scenarios where it is more effective (and sometimes the only way) to debug using real time trace, instead of relying solely on breakpoints and stepping.
The Ultra-XD supports real-time tracing for all EM and HS DesignWare processors and offers many useful features including:
- Single or multi-core capable real-time Nexus-based tracing
- Parallel trace capture from program counter, memory R/W and register R/W
- Tracing execution code, data, exceptions, interrupts etc.
- Trace filters for tracing only the areas of code and/or data of interest
- Triggering on complex, conditional conditions
Key advantages of the Ultra-XD trace probe include:
- Large capacity 4GB trace buffer for tracing large volumes of real-time data
- Non-intrusive trace capture for detecting problems during full-speed real-time execution including interrupt handlers, exceptions etc.
- Seamless integration of Synopsys MetaWare debugger and Ashling Ultra-XD trace probe provides a high- performance debug environment
About Ashling Microsystems
Ashling Microsystems is an international Embedded Software Solutions and Debug Tools company. Through its close cooperation with leading semiconductor vendors, Ashling is a world leader in the Embedded Software Development Tools market. Ashling’s development centre is in Limerick Ireland. Ashling has sales and support representatives worldwide.
Visit www.ashling.com
Related Semiconductor IP
Related News
- Synopsys DesignWare ARC Sound IP Solution First to Support the Dynamic Resolution Adaptation Audio Standard
- Synopsys Introduces Starter Kit for DesignWare ARC EM Processors
- Synopsys Introduces Dolby MS11 Decoder for DesignWare ARC Audio Processors
- Synopsys Introduces DesignWare ARC EM SEP Processor for Safety-Compliant Automotive Systems
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology