Denali offers PCI Express compliance suite
Richard Goering
(04/29/2004 5:00 PM EDT)
SANTA CRUZ, Calif. — Promising to save man-years of effort for PCI Express verification, Denali Software is introducing PureSuite, a compliance test suite with some 7,500 pre-built tests. It works with PureSpec, Denali's existing verification intellectual property (IP) for PCI Express.
Introduced a year and a half ago, PureSpec contains a bus-functional model and an assertion library, and has around 40 customers, said David Lin, Denali vice president of product management. But the assertions, he noted, depend on stimulus, and don't provide a complete check of the PCI Express specification. That's where PureSuite comes in.
PureSuite exercises PCI Express functionality and corner cases, including all items defined in the compliance checklist document from the PCI Special Interest Group (PCI SIG). It checks the physical layer, data link, transaction layer, and configuration space with both compliant and non-compliant traffic to measure error recovery capabilities.
"It tries to exercise a design in a targeted fashion against the checklist," Lin said. "I think PureSuite can save three to five man-years because all the tests are pre-built, configured, and tailored dynamically to the DUT [device under test] configuration."
Users can edit or customize tests, Lin noted, by adjusting the Specification of Modeling Architectures (SOMA) file that comes with PureSpec. For example, a user could run only the data link layer tests, or check specific compliance checklist items.
Each test includes a description of purpose, assumptions, scenario, expected result, and PCI-SIG checklist item number. The tests are written in C, and can be accessed through the Verilog programming language interface (PLI). The C language capability lets Denali support all existing verification environments, Lin said.
PureSuite works only with PureSpec and is available now at $50,000 per project. A more detailed view of PureSpec and PureSuite is provided in a All material on this site Copyright © 2005 CMP Media LLC. All rights reserved.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related News
- Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process
- PLDA Achieves PCI Express 3.0 Compliance for XpressSWITCH IP, Adding to its List of PCI Express Compliant Products
- PLDA Achieves PCI Express 4.0 Compliance for its XpressRICH PCIe Controller IP During the First Official PCI-SIG PCIe 4.0 Compliance Workshop
- Avery Design Launches PCI Express 6.0 Verification IP to Enable Early Development, Compliance Checking for New Version of Standard
Latest News
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms