DeepX Hints At Next-Gen AI Chips
By Sally Ward-Foxton, EETimes (August 30, 2024)
SANTA CLARA, Calif.—DeepX demonstrated its two first-generation chips, which are aimed at different markets, at the Embedded Vision Summit, and gave EE Times some hints on its next-generation chip for AI on-device and in autonomous robots.
Demos
The V1 (previously named L1) is an SoC with the DeepX 5-TOPS NPU alongside quad-RISC-V CPUs. It also features a 12-MP image signal processor (ISP). This is a small, sub-$10 SoC for edge devices, built on Samsung 28-nm process technology for power efficiency. DeepX’s V1 demo runs YOLO v7 at 30fps for real-time processing. Its power envelope is 1-2 W.
To read the full article, click here
Related Semiconductor IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
Related News
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- 50 TOPS DC-ROMA RISC-V AI PC is Here
Latest News
- AOMedia Announces Year-End Launch of Next Generation Video Codec AV2 on 10th Anniversary
- Altera Closes Silver Lake Investment to Become World’s Largest Pure-play FPGA Solutions Provider
- IntoPIX & Altera Unlock New Levels Of Efficiency For JPEG XS On Agilex At IBC 2025
- Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology
- Efinix® Doubles Titanium Product Line