DeepX Hints At Next-Gen AI Chips
By Sally Ward-Foxton, EETimes (August 30, 2024)
SANTA CLARA, Calif.—DeepX demonstrated its two first-generation chips, which are aimed at different markets, at the Embedded Vision Summit, and gave EE Times some hints on its next-generation chip for AI on-device and in autonomous robots.
Demos
The V1 (previously named L1) is an SoC with the DeepX 5-TOPS NPU alongside quad-RISC-V CPUs. It also features a 12-MP image signal processor (ISP). This is a small, sub-$10 SoC for edge devices, built on Samsung 28-nm process technology for power efficiency. DeepX’s V1 demo runs YOLO v7 at 30fps for real-time processing. Its power envelope is 1-2 W.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related News
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions
- Upbeat Technology and SiFive Introduce Next-Gen Ultra-Low Power RISC-V MCU with AI Acceleration
- Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded Devices
- RISC-V Exceeding Expectations in AI, China Deployment
Latest News
- Barcelona Zettascale Lab advances European technological sovereignty as Cinco Ranch TC1 chip passes validation
- CoreHW Appoints Redtree as Pan-EMEA Sales Representative
- Imec inaugurates NanoIC pilot line, accelerating innovation in sub-2nm systems-on-chip
- Honda and Mythic Announce Joint Development of 100x Energy-Efficient Analog AI Chip for Next-Generation Vehicles
- PQSecure Collaborates with George Mason University on NIST Lightweight Cryptography Hardware Research