Denali Software DDR SDRAM Controller IP and PHY Solution Integrated into STMicroelectronics' SPEAr Family of Microprocessors

High-Quality Databahn DDR3/2 SDRAM Controller and DFI-Compliant Synthesizable GHz PHY Utilized in Various eMPUs for Communication, Display and Networked Devices

SUNNYVALE, Calif., June 9, 2010 – Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that STMicroelectronics, a global leader in developing and delivering SoC and semiconductor solutions, has integrated Denali’s configurable Databahn® DDR3/DDR2 SDRAM multiport memory controller IP and DFI-compliant Synthesizable GHz PHY IP as a baseline solution for the Structured Processor Enhanced Architecture (SPEAr®) embedded microprocessor platform. STMicroelectronics’ engineers were able to meet their specific design requirements and add configurability to their chips by leveraging the Databahn controller and PHY IP for their SPEAr family of microprocessors (SPEAr600 and later). The new SPEAr1300 product line architecture provides substantial breakthrough in computing power and connectivity for networked devices and will be used for communication, display and control applications.

“We selected Denali because of its established leadership in delivering high-quality IP and PHY technology, which has been silicon-proven in a wide range of our high-performance SoC designs,” remarks Stefano Ravaglia, SoC R&D director at STMicroelectronics. “Our new-generation SPEAr family of embedded microprocessor technologies targets many of today’s computing and connectivity requirements. Denali’s Databahn controller IP and PHY can be easily implemented in our advanced HCMOS process technologies providing the marketplace with the optimal solutions to streamline embedded SoC designs.”

STMicroelectronics’ SPEAr family of microprocessors targets embedded-control applications across market segments from computer peripherals and communications to industrial automation. These devices allow equipment manufacturers to develop complex yet flexible digital engines with remarkable time and cost savings during the design cycle. STMicroelectronics’s SPEAr multi-application chips are manufactured in state-of-the-art, low-power 90, 65, and 55nm HCMOS (high-speed CMOS) process technologies and provide high levels of computing power and connectivity.

“As the leading provider in connectivity IP, we continue to provide customers such as STMicroelectronics with comprehensive, high-quality solutions that reduce design risk and enable them to develop complex chips on schedule,” commented Marc Greenberg, director, Technical Marketing at Denali Software. “We appreciate ST’s trust in Denali and welcome the opportunity to help them ramp their SoC designs to volume production faster.”

About Databahn DDR SDRAM Solutions

Denali’s Databahn configurable, high-performance memory controller ensures compatibility with all the latest high-speed SDRAM technologies, including the many DDR3/2 and LPDDR2/1 devices offered by all major memory vendors. The Databahn controller IP has been proven in all major commercial process technology nodes. Databahn controllers are DFI-compliant (DFI is the industry’s standard interface between memory controllers and PHYs), they are highly configurable, and they are easy-to-integrate into a chip design, making them an appropriate match for a wide range of system architectures. For more info, visit: www.denali.com/dram.