DARPA Looks to Automate Security for IC Design
By George Leopold, EETimes (May 27, 2020)
The latest in a series of Pentagon semiconductor initiatives seeks to embed security features into chip designs that would allow silicon architects to probe economics-versus-security tradeoffs while baking in security throughout device lifecycles.
The chip design effort represents continuing U.S. efforts to secure its electronics supply chain as semiconductors emerge as a choke point in what is shaping up as a technological Cold War with China.
DARPA announced two teams this week to ramp up its year-old Automatic Implementation of Secure Silicon (AISS) program led by Synopsys and Northrop Grumman. Both teams will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and reverse-engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips throughout their lifecycles.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Optima Launches New IC Security Verification Solution
- Digital Core Design Presents DAES XTS Cryptographic CPU for Unparalleled Security
- QC Design announces launch of fault-tolerance design automation tool Plaquette+ and first sale to QuiX Quantum
- Top Ten IC Design Houses Ride Wave of Seasonal Consumer Demand and Continued AI Boom to See 17.8% Increase in Quarterly Revenue in 3Q23, Says TrendForce
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers