DARPA推进集成电路设计安全自动化

By George Leopold, EETimes (May 27, 2020)

The latest in a series of Pentagon semiconductor initiatives seeks to embed security features into chip designs that would allow silicon architects to probe economics-versus-security tradeoffs while baking in security throughout device lifecycles.

The chip design effort represents continuing U.S. efforts to secure its electronics supply chain as semiconductors emerge as a choke point in what is shaping up as a technological Cold War with China.

DARPA announced two teams this week to ramp up its year-old Automatic Implementation of Secure Silicon (AISS) program led by Synopsys and Northrop Grumman. Both teams will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and reverse-engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips throughout their lifecycles.