Cynergy offers ARM core models for open simulation platform for embedded system software development and SoC verification

AUSTIN, TX June 12, 2001 Cynergy System Design, Inc., the leading provider of embedded system simulation solutions for hardware and software co-verification, today announced that it has signed an agreement with ARM [(LSE:ARM); (Nasdaq:ARMHY)], the industry's leading provider of 16/32-bit embedded RISC processor technology, to integrate and distribute ARM® processor core models as an option to Cynergy's ASVP Builder product.

Design teams building embedded systems with ARM processor cores, can now use Cynergy's ASVP Builder for cycle-accurate simulation of both the system-on-chip (SoC) hardware design and the software running on the SoC, to get products to market quickly.

ASVP's (Application Specific Virtual Prototypes) created with ASVP Builder are suitable for specifying RTL-based hardware component assemblies, verifying the functional accuracy of the resulting SoC designs and for co-simulating embedded software on the ASVP Builder's hardware simulator(s).

Cynergy, a member of the ARM EDA Partnership Program, is supporting members of both the ARM7T and ARM9T families of microprocessor cores. ASVP Builder's implementation as an Open Simulation Platform enables end-user integration of cycle-accurate ARM models with project-specific verification environments, third party hardware and software (HW and SW) development tools, and RTL HW component models for the verification of a complete embedded design.

"ARM's Cycle-Callable Models (CCM) complement Cynergy's Open Simulation Platform, which is enabled by the ASVP Builder product," said Jon Connell, Modeling Solutions Engineering manager, ARM. "CCMs are a new class of C model from ARM, offering high performance and cycle accuracy. They also offer a cycle-by-cycle advance capability and so are ideally suited to the clock-accurate C modeling environment provided by Cynergy's ASVP Builder."

"By making industry-leading ARM cores available within an Open Simulation Platform, customers can develop more reliable ARM core-based SoC designs in less time," said Prem Jain, founder and CEO of Cynergy System Design. "The combination of ARM and Cynergy enables our joint customers to design SoCs without the architectural limitations imposed by other co-verification solutions. The user-programmability of our environment allows internally-developed or externally acquired C verification environments to be integrated with fully-integrated clock-accurate system-IC C models including the ARM core models. This demonstrates how existing CPU C models are easily integrated into open simulation platforms."

Both ASVP Builder and the ARM core model options are available from Cynergy now.

About the ARM EDA Partnership Program
The ARM EDA Partnership Program brings together ARM's expertise in reusable intellectual property (IP) generation and IP modeling, with the EDA design methodology expertise of leading EDA tool vendors to develop faster, more accurate routes to SoC products.
The Program establishes a framework of co-operation between engineering teams. The goal is to specify a range of core models, or IP views, that are developed by ARM as an integral component of the internal IP generation flow.

About Cynergy
Cynergy System Design, Inc. is the premier provider of solutions for early and accurate simulation of embedded systems to companies developing SoC and other embedded system products. Cynergy's solutions reduce design iterations and accelerate time-to-market for embedded system applications. Using Cynergy's products, embedded developers can create ASVPs for simulation early in the SoC design process. For more information please call 512.338.0165, or visit Cynergy's website at www.cynergysd.com.
 
 
 

For more information, contact:

For ARM
Michelle Spencer
ARM
michelle.spencer@arm.com
Tel: +44 1628 427780
For Cynergy
Georgia Marszalek
Valley PR
georgia@valleypr.com
Tel: (650) 345 7477
 
 

Acronyms

API Application Programming Interface
ASVP Application Specific Virtual Prototype
CCM Cycle-callable Model
EDA Electronic Design Automation
HW Hardware
RISC Reduced Instruction Set Computing
RTL Register Transfer Level
SoC System-on-a-chip
SW Software