CXL Fulfills AI's Need for Open Industry Standard Interconnect
By Debendra Das Sharma , EETimes (July 16, 2024)
We have been in a virtuous cycle of innovation for decades now where dramatic improvements in compute capability—primarily driven by extraordinary advances in transistor and process technologies—have enabled diverse applications. These applications, including generative-AI, are driving an insatiable demand for heterogeneous computing, memory bandwidth, memory capacity and interconnect bandwidth to satisfy the demand of applications.
The need for a robust interconnect standard
While PCIe is a great interconnect, emerging data-centric applications pose a new set of challenges requiring enhancements to PCIe:
- High-performance heterogeneous computing with shared coherent memory space.
- Overcoming the memory bandwidth bottleneck of DDR parallel bus and providing tiered cost-effective memory support.
- Minimizing stranded resources in data centers by pooling memory and accelerators across multiple servers.
- Enabling distributed computing through low-latency load-store-based message passing and shared memory across a large pool of servers, including coherent near in-memory compute.
To read the full article, click here
Related Semiconductor IP
- CXL 3.0 Controller
- CXL Controller IP
- CXL memory expansion
- CXL 3 Controller IP
- CXL 4.0/3.2/3/2 Verification IP
Related News
- Eliyan Applauds Release of OCP's Latest Multi-die Open Interconnect Standard, BoW 2.0
- Key Industry Players Converge to Advance CXL, a New High-Speed CPU Interconnect for Breakthrough Data Center Performance
- Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard
- PLDA Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL, PCIe 6.0 or Gen-Z Interconnect
Latest News
- Quintauris and Andes Technology Partner to Scale RISC-V Ecosystem
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
- Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- TSMC September 2025 Revenue Report
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions