Creonic Introduces Doppler Channel IP Core
Kaiserslautern, Germany, January 14, 2025 - Creonic GmbH, the leading provider of cutting-edge communications IP cores, proudly announces the release of its Doppler Channel IP core. Designed to meet the growing demand for efficient and accurate Doppler shift emulation in Low Earth Orbit (LEO) communication systems, this innovative solution accelerates system performance evaluation while maintaining exceptional accuracy.
The Creonic Doppler Channel IP core generates Doppler shift frequencies by precisely adjusting the phase of signal samples in real-time. The IP core supports orbital heights ranging from 200 to 2000 km and accommodates carrier frequencies in L-band (S-band, X-band and Ka-band on request) making it ideal for modern LEO communication scenarios.
With a throughput of up to 0.62 GSPS at 620 MHz and a latency of just 78.98ns, the Doppler Channel IP core ensures fast and reliable processing. Its design-time configuration and use of the fast inverse square root algorithm enhance accuracy while keeping complexity and power consumption low. Applications for this IP core include LEO digital communication systems where accurate Doppler channel modeling is required. The hardware-based approach significantly reduces runtime compared to traditional software based methods, achieving results in a fraction of the time.
Seamless integration is made possible through AXI4- Stream handshaking interfaces, and the core is compatible with ASIC and FPGA technologies, including platforms from AMD Xilinx, Intel Altera and Microchip.
Related Semiconductor IP
- Fixed Point Doppler Channel IP core
- 1.8 to 3.6V output, 0.9V to 1.8V input voltage doubler
- Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
- Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
- Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Related News
- Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
- Creonic Introduces FEC IP Core Solution for SDA Free-Space Optical OCT V3.0 Standard
- Creonic Introduces 25 Gbit/s LDPC IP Core Solution for ITU G.9804.2 PON Standard
- Creonic Releases Ultrafast BCH Decoder IP Core, Processing One Codeword per Clock Cycle
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack