Common Platform in Preparation for SOI, FinFETs at 10nm
Peter Clarke, Electronics360
08 April 2014
A team of engineers from IBM Microelectronics, Globalfoundries, Samsung, STMicroelectronics and UMC are due to present a 10nm logic platform that supports FinFETs on both bulk CMOS and on silicon-on-insulator wafers.
The presentation of paper 2.2 is set to be one of the highlights of the Symposium on VLSI Technology due to take place June 9 to 12 at Honolulu, Hawaii. It represents a coming together of the interests of the FinFET and fully-depleted silicon-on-insulator (FDSOI) camps, but not yet a complete merging.
To read the full article, click here
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related News
- TSMC Certifies Synopsys IC Compiler II for 10-nm FinFET Production and 7-nm Early Design Starts
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- Silicon Creations Taps Silvaco's Custom Design Flow for 10nm FinFET Designs
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
Latest News
- Kandou AI Secures Strategic Funding to Redefine AI Connectivity and Break Memory Bottlenecks in AI
- CEA-Leti and Fraunhofer IPMS Validate Wafer Exchange for Ferroelectric Memory Materials Within the FAMES Pilot Line
- How GlobalFoundries Takes AI from Pilot to Global Scale
- Jmem Tek Joins GlobalFoundries Ecosystem to Expand Post-Quantum Security Solutions
- TES Unveils High-Performance 8/40MHz Oscillator and Clock Buffer IPs for Reliable On-Chip Timing Solutions for X-FAB XT018 - 0.18µm BCD-on-SOI technology