Shift in the integration equation
Bill Schweber -- EE Times
(12/24/2007 9:00 AM EST)
The trend of the semiconductor road map has always been to pack more functions on a single die through process shrinks and better processing, bolstered by a larger die itself. This is especially true on the digital side, where economies of scale are easily defined: early CPUs soon expanded to include various types of I/O, buffers, memory and more. But it has also been true on
the analog side, as the "complete" 12-bit D/A converter led to the "really complete" DAC with integrated output buffer and then the "really, truly complete" DAC with internal voltage reference.
At a recent meeting with a leading linear-IC vendor, however, engineers noted that chip-scale packaging (CSP) technologies may be upsetting this IC road map axiom.
(12/24/2007 9:00 AM EST)
The trend of the semiconductor road map has always been to pack more functions on a single die through process shrinks and better processing, bolstered by a larger die itself. This is especially true on the digital side, where economies of scale are easily defined: early CPUs soon expanded to include various types of I/O, buffers, memory and more. But it has also been true on
the analog side, as the "complete" 12-bit D/A converter led to the "really complete" DAC with integrated output buffer and then the "really, truly complete" DAC with internal voltage reference.
At a recent meeting with a leading linear-IC vendor, however, engineers noted that chip-scale packaging (CSP) technologies may be upsetting this IC road map axiom.
To read the full article, click here
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- CAN-FD Controller
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- Lattice Announces New Automotive Qualified Chip Scale 132 BGA Packaging for the LatticeXP2 Family
- Geopolitical Tensions Fuel a Wave of AI Chip Independence as US and Chinese CSPs Race to Develop In-House ASICs, Redefining the Market Landscape, Says TrendForce
- LSI Logic licenses packaging technology to Taiwan firm
- Dense-Pac applies chip-stacking packaging to DSPs
Latest News
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology