Calypto Delivers Bus Interface Libraries to Easily Connect High Level Synthesis Models to ARM Platform
SANTA CLARA, Calif., – February 27, 2012 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced bus interface libraries that connect hardware subsystems implemented with Calypto’s High Level Synthesis product (HLS), Catapult® Synthesis, with AMBA® AXI™ bus interfaces. The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. The highly parameterizable AXI interface supports a wide range of configurations including burst modes, bus width and auxiliary control signals.
“The AXI interfaces are the first in a series of libraries in development at Calypto that will make Catapult C more readily available to mainstream designers," said Shawn McCloud, Vice President of Marketing at Calypto. “They are written entirely in SystemC and tuned through the Catapult C synthesis tool. These interfaces are a great example of the benefits of mixing cycle accurate SystemC for control with abstract SystemC/C++ to implement a hardware subsystem.”
The AXI interface library is tuned so the resulting hardware is optimized for the user’s specific performance requirements, configuration mode and target technology. Availability in April, please contact Calypto Sales for specific pricing and information.
About Calypto’s Products
Catapult High Level Synthesis, Calypto’s SLEC® (Sequential Logic Equivalence Checking) and PowerPro® platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable electronic system level design by engineers to dramatically improve design quality and reduce power consumption of their system-on-chip (SOC) devices.
About Calypto
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.
Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
More information can be found at www.calypto.com.
Related Semiconductor IP
- CXL 3.0 Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- PCIe 6.0 (Gen6) Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
Related News
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
- Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker
- MulticoreWare collaborates with Arm to optimize and advance x265 video encoding on AWS Graviton4
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology