Cadence and Rapidus Collaborate on Leading-Edge 2nm Semiconductor Solutions for AI and HPC Applications
Collaboration spans interface and memory IP utilizing 2nm gate-all-around BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips
SAN JOSE, Calif.— December 10, 2024 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced it is collaborating with Rapidus Corporation to provide co-optimized AI-driven reference design flows and a broad IP portfolio to support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from Rapidus’ backside power delivery network (BSPDN) technology. As the semiconductor industry struggles to keep up with significantly increasing design challenges driven by the need for more computation, GAA and BSPDN manufacturing technologies are becoming vital to meet increasingly stringent power, performance and area requirements.
The AI-driven digital and analog/mixed signal reference design flows encompass numerous solutions from Cadence, including Cadence ® Cerebrus ™ Intelligent Chip Explorer , Cadence JedAI Solution, Genus ™ Synthesis Solution , Conformal ® , Joules ™ RTL Power Solution , Innovus ™ Implementation System , Tempus ™ Timing Signoff Solution , Quantus ™ Extraction Solution , Voltus IC Power Integrity Solution ™ , Virtuoso ® Studio , Spectre ® X Simulator , Voltus ™ -XFi Custom Power Integrity Solution , and Pegasus ™ Verification System . Customers will be able to use a broad portfolio of Cadence interface and memory IP components, including HBM4, 224G SerDes, and PCI Express ® (PCIe ® ) 7.0 .
“Our collaboration with Cadence on 2nm BSPDN technology puts us at the industry’s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we’re excited to set new technology standards and create transformative solutions for our mutual customers and the industry,” said Dr. Atsuyoshi Koike, CEO of Rapidus.
“Our broad collaboration with Rapidus for 2nm GAA BSPDN technology leverages Cadence’s AI-driven solutions to solve real-world problems and meet customer needs,” said Dr. Anirudh Devgan, president and CEO at Cadence. “By bringing together Cadence’s advanced interface and memory IP technology, reference flows and Rapidus’ process technology, we're empowering the buildout of the AI infrastructure of tomorrow.”
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. For 10 years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
Related Semiconductor IP
- 224G-LR SerDes PHY enables 1.6T and 800G networks
- HBM4 Memory Controller
- HBM4/3E Combo PHY & Controller
Related News
- Rapidus Announces Strategic Partnership with Quest Global to Enable Advanced 2nm Solutions for the AI Chip Era
- Cadence Enables Next-Gen AI and HPC Systems with Industry’s Fastest HBM4 12.8Gbps IP Memory System Solution
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Consortium forms Rapidus to get Japan back into chip race at 2nm
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale