The fourth-generation and third-generation HBM (HBM4/3E) technology is outlined by the JESD238A standard (for HBM3E) and an upcoming specification (for HBM4). These technologies feature 256-bit memory access per channel, with a 1024-bit input/output interface for HBM3E and up to a 2048-bit interface for HBM4. The I/O voltage is 0.4 V for HBM3E, while HBM4 further reduces this. Similar to previous generations, HBM4/3E supports two, four, eight, twelve, or sixteen DRAM devices on a base logic die (2Hi, 4Hi, 8Hi, 12Hi, 16Hi stacks) per KGD. HBM3E expands the capacity of DRAM devices within a stack to 48GB, and increases the data rate to up to 9.6Gbps per pin.
HBM4/3E Combo PHY & Controller
Overview
Key Features
- Compliant with JEDEC Specification, up to 10Gbps
- Compliant with DFI 4.0 Specifications (dfi_clk_1x : WDQS = 1:4)
- Supports up to 16 channels with 64-bit DQ-width + Optional DBI/ECC/SEV pin support/channel for HBM3E
- Supports up to 32 channels with 64-bit DQ-width + Optional DBI/ECC/SEV pin support/channel for HBM4
- Supports command and DQ parity
- Supports per-AWORD de-skew tuning for command
- Supports bit-group de-skew tuning for data
- Supports CMD/DQ lane repair
- Supports auto and software Command Bus Training, RX DQS Training and Bypass RX DQS Control, WDQS2CK Training and Bypass WDQS2CK Control, Read/Write Training and Bypass Read/Write Training
- Supports auto retraining mode and retraining bypass mode
- Supports ZQ calibration
- Supports Built-In Self-Test
- Supports multiple DFT methods:
- At-speed Scan
- Stuck-at Scan
- Boundary Scan
- Supports various power-down modes for low power:
- Stop clock low-power mode
- DFI low-power interface
- APB 3.0 interface to configure registers
- Supports IEEE1500 port for direct access to the memory stack and PHY using APB
- Supports HBM DRAM initialized by PHY
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues in testing
Benefits
- Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
- Zero risk with robust ESD architecture
- Extensive EDA tool support for various design and automation flow
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
- Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing
Block Diagram
Deliverables
- Extensive documentation
- Models
- LIB
- LEF
- Place-and-route abstracts
- LVS netlist
- GDSII files