Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025

Revolutionary Technology Bridges Pre- and Post-Optimization Design Flows with Automated SDC Management

SAN FRANCISCO-- June 23, 2025 -- Ausdia, the leading provider of design constraints verification and management solutions, today introduced Timevision^TM OneSource, at DAC 2025, the Chips to Systems Conference.

Timevision OneSource addresses a critical challenge facing modern SoC design teams while maintaining the integrity and usability of hand-crafted timing constraints after optimization tools perform aggressive transformations on chip designs.

The OneSource technology addresses the fundamental challenge created by modern optimization engines that dissolve hierarchies, restructure interfaces, duplicate elements, and perform advanced transformations like flop banking and cloning. These optimizations, while delivering significant PPA improvements, render original programmatic SDC constraints unusable in their original form.

"The shift-left methodology has led design teams to create sophisticated, programmable constraint files that map correctly and consistently on their original RTL designs," said Sam Appleton, Ausdia CEO. "However, when optimization tools restructure hierarchies, merge flops, and clone elements to achieve better PPA, those golden constraints no longer map to the transformed design. OneSource solves this critical gap by automatically translating source constraints to work seamlessly with post-optimization netlists."

Automated Constraint Translation Without Manual Intervention

Timevision OneSource enables design teams to retain their golden, hand-written SDC constraints throughout the entire design flow. The technology automatically generates a new version of block-level constraints that can be used for full-chip signoff, eliminating the time-consuming and error-prone manual constraint adaptation process that is plaguing post-optimization flows.

OneSource maintains two critical capabilities that design teams require: Porting source-form constraints so engineers have full confidence in their signoff checks, and automatically generating chip-level constraints for the post-optimization database without designer intervention.

Key Benefits of OneSource:

• Automated translation: Eliminates manual constraint adaptation after optimization
• Source preservation: Maintains readable, understandable constraint files for design signoff
• Full-chip compatibility: Automatically generates constraints compatible with post-optimization netlists
• Quality assurance: Provides verification and validation of constraint translation accuracy
• Design flow integration: Seamlessly bridges pre- and post-optimization environments

"OneSource represents a breakthrough in constraint management technology," Appleton said. "Design teams no longer need to choose between achieving optimal PPA through advanced optimization and maintaining clean, understandable constraints. Our solution delivers both automatically."

Comprehensive Integration with Timevision Platform

OneSource integrates seamlessly with the existing Timevision platform, leveraging its comprehensive timing constraints development, verification, and management capabilities. The platform continues to support more than 1 billion cells and thousands of clocks, integrating with all aspects of the design flow from pre-synthesis through signoff timing.

About Timevision

Ausdia’s Timevision platform offers a unique approach to timing constraints development and management, addressing key challenges in AI and large SoC designs, including memory consumption and performance optimization.

Ausdia is showcasing the enhanced Timevision platform, including the new OneSource technology, in booth #2429 at DAC, The Chips to Systems Conference, held at Moscone West, San Francisco, from June 22-25 2025.

About Ausdia

Founded in 2006 and headquartered in Sunnyvale, California, Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. Ausdia’s customers include leading semiconductor companies worldwide, and the company’s solutions are used extensively in the development of SoCs and ICs for AI, HPC, and automotive. For more information, visit Ausdia’s website.