Atrenta adds design-for-test analysis to SpyGlass tool
Atrenta adds design-for-test analysis to SpyGlass tool
By Michael Santarini, EE Times
January 8, 2002 (2:21 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020108S0055
SAN MATEO, Calif. Atrenta Inc. has introduced added a design-for-test analysis capability to its SpyGlass predictive analysis tool. The DFT add-on gives SpyGlass a cycle-accurate simulation engine and a testability analysis engine, said Ghulam Nurie, senior vice president of marketing and business development at Atrenta. That capability lets users enter constraints to find early in the design cycle, during RTL development problems that could occur in the manufacturing test phase. The DFT add-on, Nurie said, ensures that designers will write their RTL code to comply with testability rules early on, before they run synthesis and simulation cycles. Finding these problems at the beginning of the design process can save several iterations and cut weeks off design cycles, he said. "Trying to predict testability problems early in the design cycle is a difficult problem because testability is really a structural problem, not a functional problem," said Nurie. "Typically, you can't tell if you have a structural problem with RTL until you synthesize it. Our unique technique allows SpyGlass to do it." Nurie said that after the tool runs through synthesis as usual, it then does cycle-accurate simulation on the gate-level netlist in test and scan mode. The testability analysis then checks the design against user constraints. Errors are highlighted and called out in the user's RTL code. "We added a simulation engine because some test issues require dynamic analysis," said Nurie. "The testability engine does a true controllability and observability analysis of every signal in the design." Nurie said his company has worked with Logic Vision, and correlated its offering with that company's test tools. Atrenta plans to work with other test vendors to add SpyGlass DFT rules to their test tools, he said. SpyGlass 3.0 starts at $60,000 per year for an entry package. The tool runs on Sun/Solaris 2.5-2.8, HP-UX 10.2 and Red Ha t Linux 6.2 and above operating systems. The SpyGlass DFT option is priced at $25,000 per year.
Related Semiconductor IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
Related News
- Atrenta's SpyGlass SoC Addresses Logic Integration Issues that Plague IC Design Efforts
- The Microwave Division of Siemens Italy Selects Atrenta's SpyGlass to Implement Design Reuse and Best Practices Policy
- Atrenta's SpyGlass Wins Prestigious "LSI Design of the Year" Award
- Agere Systems Provides Atrenta's SpyGlass to Customers for Comprehensive ASIC Handoff
Latest News
- Rambus Unveils HBM4E Controller: 16 GT/s, 2,048-Bit Interface, Enabling C-HBM4E
- AimFuture, a Leader in Home Appliance NPUs, to Integrate Mesacure Company’s AI Algorithms
- Security in the Quantum Era: From Cryptography to Trust — ICTK Introduces a Hardware Trust Foundation for the Quantum Era
- TES unveils a next-generation Elliptic Curve Digital Signature Algorithm (ECDSA) IP Core for Secure IoT, Blockchain, and Industrial Systems
- Seligman Ventures Leads Cognichip’s $60M Series A to Back Physics-Informed AI for Chip Design, Intel CEO Lip-Bu Tan and Seligman Ventures’ Umesh Padval Join the Board