Ashling launches initiative on multi-core SoC debugging

San Francisco, California, March 13, 2002: At the Embedded Systems Conference in San Francisco today, Ashling Microsystems launched a Multi-core Debugging Initiative which it hopes will result in the creation of an industry forum to develop standards for debug of multi-core based Systems-on-Chip (SoCs). Continuous innovation in products based on embedded systems means that designers of embedded silicon are under constant pressure to improve processing power, reduce power consumption, and reduce size, cost, and time-to market. Integrating the disparate silicon elements of an embedded system onto a single chip (System-on-Chip, or SoC) is a highly effective means to achieve all of these objectives, but at the cost of an almost overwhelming increase in system complexity. Thus, an effective debug methodology is an indispensable route to managing this design complexity. Debugging and integrating complex multi-core SoC applications requires debug and integration solutions that are substantially more powerful than the traditional combination of single source-debuggers, an external Emulator and on-chip Debug interface. In particular, the debug environment must control, monitor, display and visualize the complex series of interactions among multiple cores, and must reflect, overall, the design methodology with which the system was created. Through discussions with silicon vendors, IP vendors and strategic users it is apparent that the increase in SoC complexity needs a new solution for multi-core debug. Strategic users and vendors have a common interest in defining a multi-core debug architecture and standards. Hence, Ashling is inviting feedback from the industry towards a solution by announcing this initiative. Commenting on the initiative, Hugh O’Keeffe, VP of R&D at Ashling said “Complexity, variety and scope of the SoC debug problem means that no one silicon vendor or tools vendor can provide a durable solution. In our view, the task requires industry wide cooperation and exchange of ideas to provide a durable solution. The experience of NEXUS global debug standard group shows that silicon vendors, tools vendors and end users can cooperate to define standards. We want to sit down with the leading actors in Multi-core SoC – the users, IP vendors, Tool vendors, Integrators and Silicon vendors to understand the problem and the solutions. We fully intend to share our proposals and our perspectives and work with the community to define solutions” About Ashling Microsystems: Ashling Microsystems (founded in 1985) designs and manufactures In-Circuit Emulators, JTAG/BDM Emulators, Smart Card development tools, source debuggers and Software Quality Assurance tools. Ashling's major-account customers include Motorola, Delphi Delco, Alcatel, IBM, Gemplus, Xerox, Sony, Lexmark, Visa, Hewlett-Packard, GE and Eaton. Ashling’s R&D Center is in Limerick, Ireland. The company’s North America Sales and Support Center is in Sunnyvale, California, with sales subsidiaries in the United Kingdom and France and distributors throughout the world. Editorial Contact: Ashling Michael Healy Ashling Microsystems, Inc. 1270 Oakmead Parkway, Ste. 208 Sunnyvale, CA 94085 Tel: (408) 732 6490 Fax: (408) 732 6497 Email: michael.healy@ashling.com Product Information Contact: Ashling Hugh O’Keeffe Ashling Microsystems National Technological Park Limerick Ireland Tel: +353-61-334466 Fax: +353-61-334477 Email: hugh.okeeffe@ashling.com