ARM, Improv to optimize DSP core for on-chip bus, create co-simulation system
ARM, Improv to optimize DSP core for on-chip bus, create co-simulation system
By Semiconductor Business News
December 10, 2001 (4:21 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011210S0063
CAMBRIDGE, England -- ARM Ltd. and Improv Systems Inc. today announced plans to collaborate in development of a configurable digital signal processor (DSP) core, which will be available for licensing and optimized for use on ARM's AMBA Multi-layer AHB on-chip interconnect bus. The project will allow system-on-chip developers to quickly link Improv's Jazz DSP technology with ARM's RISC microprocessors, said the two companies, which are extending their collaboration. A co-simulation system is also being developed to allow developers to verify hardware and software working together on an integrated platform. ARM here and Improv in Beverly, Mass., had earlier cooperated in creating the AHB specification and a reference platform for voice-over-packet designs. The Multi-layer AHB is a key advancement in the capabilities of AMBA interconnect, providing a solution that reduces latencies and increases the bus bandwidth available to multi-master syst ems, said officials with the two companies. "Improv and ARM have already demonstrated the benefits of combining our technologies on an SoC platform," said Cary Ussery, president and CEO of the Massachusetts company. "This integration will provide designers an even more efficient and flexible way to leverage our configurable methodology into AMBA interconnect-based designs." The work on a joint-verification environment will link the ARM and Improv simulation and debugging capabilities. Verifying actual software on the hardware design prior to prototype will increase the confidence that the system will operate as expected when manufactured, said the two companies. The AMBA Multi-layer AHB support and co-verification environment will be available from Improv during the first half of 2002.
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- Improv Jazzes up DSP core for ARM on-chip bus
- VisualSim Antenna System Designer enables simulation of Antenna and Communication Systems
- Siemens to demonstrate first pre-silicon simulation environment for Arm Cortex-A720AE for Software Defined Vehicles
- Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data