Arasan Announces immediate availability of its I3C Host / Device Dual Role Controller IP
Aug 29, 2024, San Jose, CA -- Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its I3C Dual/Secondary Controller IP which now includes the I3C PHY IP.
Arasan expands its MIPI IP portfolio with the announcement of the immediate availability of its I3C Dual/Secondary Controller IP including I3C PHY compliant with MIPI I3C HCI Specification (v1.2).
The I3C PHY supports the Ternary and non Ternary modes and is available on foundry nodes from 28nm to 4nm.
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic. The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices. In some applications, the active controllers can hand-off the controller role to the secondary controller on the bus. The Dual role IP joins the I3C bus as a secondary controller (as a target) and will request/accept the controller role. The IP core provides a 32bit AHB bus as an application interface to configure and control the transfers. The controller manages the control signal to IO buffers during the active and standby mode.
The I3C Dual Role controller is available for immediate licensing.
About Arasan:
Arasan Chip Systems is a leading provider of IP for mobile storage and mobile connectivity interfaces, with over a billion chips shipped with our IP. Our high-quality, silicon-proven Total IP Solutions encompass digital IP, Analog Mixed Signal PHY IP, Verification IP, HDK, and Software. With a strong focus on mobile SoCs, we have been at the forefront of the “Mobile” evolution since the mid-90s, supporting various mobile devices, including smartphones, automobiles, drones, and IoT devices, with our standards-based IP.
Related Semiconductor IP
- I3C Host Controller
- MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
- I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
Related News
- Arasan to demonstrate its I3C Host and Device IP and participate at the I3C Interoperability Session at the 2018 MIPI Devcon in Seoul
- Arasan Announces MIPI I3C IP Cores compliant to the MIPI I3C Specifications v1.1
- USB 4.0, USB 3.2, USB 3.1, USB 3.0, USB 2.0, Device, Hub, Host & Dual Mode proven Interface IP Controllers are available immediately to License
- Arasan Chip Systems announces Immediate availability of MIPI I3C PHY I/O IP
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing