Arasan Announces Industry's First MIPI C-PHY HDK
San Jose, CA -- Dec 5, 2017 -- Arasan Chip Systems, a leading provider of IP for semiconductor design and manufacturing, today announced availability of its MIPI C-PHY[SM] HDK built using an Arasan C-PHY ASIC. The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz and D-PHY v1.2 also with speeds of up to 2.5GHz. Arasan’s HDK offers the fastest and surest path for companies looking to adopt the latest MIPI standards. The HDK is part of Arasan’s Total IP Solution for MIPI.
The C-PHY HDK board will be assembled with either a C-PHY TSMC 28nm or TSMC 12nm ASIC.
This HDK enables customers to prototype their C-PHY based projects using Arasan’s MIPI DSI or CSI IP Cores and software stacks. The HDK can be easily integrated with Xilinx based FPGA platforms using a FMC Connector. After prototyping, the entire design can be licensed including the MIPI C- PHY / D-PHY combo IP GDS II, MIPI CSI or DSI Verilog RTL and firmware.
Arasan’s C-PHY IP has been adopted extensively by automobile, drone and imaging SoC manufacturers. Arasan is a TSMC OIP partner supporting physical interface IP for MIPI, JEDEC, ONFI, USB and SD. The C-PHY HDK board will be assembled with either a C-PHY TSMC 28nm or TSMC 12nm ASIC.
Availability
Arasan CPHY HDK is available for immediate sale. Due to high demand, the lead time for delivery is 4-6 weeks from order date with a minimum order quantity of 12 boards.
Related Semiconductor IP
- MIPI C-PHY
- MIPI C-PHY
- MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
- MIPI CPHY v1.1 Analog Interface
Related News
- Arasan announces the immediate availability of its MIPI C-PHY / D-PHY Combo IP for SoC Designs on TSMC 22nm Process
- Arasan announces its next generation of C-PHY/ D-PHY Combo IP Core compliant with the latest MIPI Specifications
- Arasan Partners with Testmetrix on its 4.5 GSPS C-PHY / D-PHY HDK and Compliance Test Platform
- Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds
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