AMIQ EDA Updates UVM Rule Checks for Latest Release of the Universal Verification Methodology Standard
June 24, 2021, San Jose, California — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced that it has expanded the rules checked by its Verissimo SystemVerilog Testbench Linter to match the latest release (IEEE 1800.2-2020) of the Universal Verification Methodology (UVM) standard. These rules ensure that chip verification teams are fully compliant in their development of simulation models, testbenches, and tests.
This standard defines an application programming interface (API) used by verification engineers. The latest release expands the API to add functionality, and Verissimo includes rule checks for these new features as well some more subtle changes in the API. In addition, IEEE 1800.2-2020 has removed some outdated parts of the API, while marking other as “deprecated” and slated for removal in the future. Verissimo alerts verification engineers when they use deleted or deprecated functionality.
When Verissimo detects code that is not compliant with the latest standard, it proposes possible fixes for the verification team to consider. These suggestions provide assistance when writing new code and make it much easier to migrate old testbenches to the latest UVM version. All rule checks can be run in batch mode using Verissimo or interactively within the AMIQ EDA Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE).
“The UVM, like many standards, evolves significantly with each new version,” said Cristian Amitroaie, CEO of AMIQ EDA. “We are pleased to ensure that our users remain compliant by avoiding outdated aspects of the API while helping them to use new functionality quickly and easily.”
Availability and Pricing
The new features are available today in Verissimo. Pricing is available upon request.
About AMIQ EDA
AMIQ EDA provides design and verification engineers with platform-independent software tools that enable them to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices. Its solutions, DVT Eclipse IDE, DVT Debugger, Verissimo SystemVerilog Testbench Linter, and Specador Documentation Generator have been adopted worldwide. AMIQ strives to deliver high quality solutions and customer service responsiveness. For more information about AMIQ EDA and its solutions, visit www.amiq.com and www.dvteclipse.com.
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related News
- Silicon Library Adopts Averant's Solidify Automated Checks Using CDC Inc. EDA Cloud Services
- AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation
- AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports First Release of Accellera Portable Test and Stimulus Standard (PSS)
- AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation