Altera's Triple-Speed Ethernet MegaCore Function Successfully Completes UNH-IOL Conformance Testing
San Jose, Calif., April 3, 2007—Altera Corporation (NASDAQ:ALTR) today announced that its Triple-Speed Ethernet MegaCore® function has successfully verified compliance with the IEEE 802.3 specification by the University of New Hampshire InterOperability Laboratory (UNH‑IOL). In addition to the MAC and 1000 BASE-X PCS test suites, the Triple-Speed Ethernet MegaCore function, implemented on Stratix® II and Stratix II GX devices, passed the independent lab’s point-to-point interoperability, auto-negotiation and flow control test suites.
“Devices with Gigabit Ethernet are scaling to support larger, more demanding and varied network architectures,” said Michael Henninger, UNH-IOL Gigabit Ethernet consortium manager. “It’s reasonable to assume that products undergoing thorough testing at a foundational level are better prepared to reliably deliver data across these networks.” The UNH-IOL is devoted to testing and debugging products for interoperability and conformance to standards in various facets of networking. For more information, visit the UNH-IOL website at www.iol.unh.edu.
The Altera® Triple-Speed Ethernet MegaCore function addresses applications ranging from telecom to medical to industrial automation. Customers can utilize Altera’s SOPC Builder system integration tool to accelerate integration of the MegaCore function with the Nios® II embedded processor to build both control and data plane applications.
“UNH-IOL conformance testing of the Triple-Speed Ethernet MegaCore function is a significant milestone in Altera’s continued commitment of enabling customers to rapidly build Ethernet solutions.” said Steve Mensor, senior director, IP and technology marketing at Altera.
Learn More at Embedded Systems Conference Silicon Valley
A demonstration of the Triple-Speed Ethernet MegaCore function will be shown by Altera in booth 1738 during the Embedded Systems Conference (ESC) in San Jose, on April 3 to 6. The Altera booth will also include demonstrations of the Nios II embedded processor, the recently announced Cyclone® III and Stratix III FPGAs, and the latest advances in SOPC Builder system development tools. Additionally, at Altera's open forum area, designers can learn how Altera and their partners offer the ultimate in embedded design versatility.
About Altera
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- UNH-IOL Meets Industry Need for 50, 100, 200 and 400 Gigabit Ethernet Testing Services
- GDA Technologies Introduces Industry’s First UNH -IOL Compliance Validated 10Gigabit Ethernet MAC IP Core for ASIC and FPGA Based Systems
- Xilinx Completes Successful UNH Interoperability Testing For Ethernet Solutions Suite With Virtex-II Series FPGAs
- Arasan Chip Systems Completes UNH Interoperability Testing for 10/100 Ethernet Solutions Suite
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications