Altera Reveals Stratix 10 Innovations Enabling the Industry’s Fastest and Highest Capacity FPGAs and SoCs

San Jose, Calif., June 8, 2015 – Altera Corporation (Nasdaq: ALTR) today revealed architectural and product details of its Stratix^® 10 FPGAs and SoCs, the next generation of high-end programmable logic devices delivering breakthrough levels of performance, integration, density and security.

Stratix 10 FPGAs and SoCs leverage Altera’s revolutionary HyperFlex^™ FPGA fabric architecture built on the Intel^® 14 nm Tri-Gate process to provide 2X higher core performance over previous generation FPGAs. Combining the industry’s highest performance, highest density FPGA with advanced embedded processing capabilities, GPU-class floating point computation performance and heterogeneous 3D SiP integration, enables Altera customers to uniquely address design challenges in the next generation of communications, data center, IoT infrastructure, military and high-performance computing systems.

“The capabilities that we offer in Stratix 10 FPGAs and SoCs are truly unmatched in the industry,” said Danny Biran, senior vice president of marketing at Altera. “Stratix 10 FPGAs and SoCs will enable our customers to design their systems and innovate in ways that were previously not possible in an FPGA.”

HyperFlex Architecture “Registers Everywhere” Approach
Stratix 10 FPGAs and SoCs are the first Altera devices to leverage the company’s new HyperFlex architecture, the FPGA industry’s most significant fabric architecture innovation in over a decade. The HyperFlex architecture, along with a full process node advantage from the Intel 14 nm Tri-Gate process, provides a 2X core logic frequency improvement over competing next-generation high-end FPGAs.

The HyperFlex architecture introduces registers throughout all core interconnect routing segments, enabling Stratix 10 FPGAs and SoCs to benefit from proven performance-enhancing design techniques such as register retiming, pipelining and other design optimization techniques. These design techniques are not practical in conventional FPGA architectures. The HyperFlex architecture allows designers to eliminate critical paths and routing delays, and rapidly close timing on their designs. The ability to achieve 2X higher core logic performance also enables dramatic improvements in device utilization and power by reducing the need for very wide data paths and other skew-inducing design constructs required by competing architectures. The HyperFlex architecture enables high-performance designs to operate up to 70 percent lower power by reducing logic area requirements. Find more information at www.altera.com/hyperflex.

A New Era of Heterogeneous 3D System-in-Package Integration
All members of the Stratix 10 FPGA and SoC family leverage heterogeneous 3D SiP integration to efficiently and economically integrate a high-density monolithic FPGA core fabric (up to 5.5M logic elements) with other advanced components, thereby increasing the scalability and flexibility of Stratix 10 FPGAs and SoCs. A monolithic core fabric maximizes device utilization and performance by avoiding the connectivity issues of competing homogeneous devices that use multiple FPGA die to deliver higher densities. Altera’s heterogeneous SiP integration is enabled through the use of Intel’s proprietary EMIB (Embedded Multi-die Interconnect Bridge) technology, which provides higher performance, reduced complexity, lower cost and enhanced signal integrity compared to interposer-based approaches.

Initial Stratix 10 devices will use EMIB to integrate high-speed serial transceiver and protocol tiles with monolithic core logic. Implementing high-speed protocols and transceivers through a heterogeneous 3D SiP approach will allow Altera to rapidly deliver Stratix 10 device variants that address evolving market demands. For example, the use of heterogeneous 3D SiP integration provides Stratix 10 devices a path to support higher transceiver rates (56 Gbps), emerging modulation formats (PAM-4), communications standards (PCIe Gen4, Multi-Port Ethernet), and other capabilities such as analog or high-bandwidth memory.

All densities in the Stratix 10 family will be available with an integrated 64-bit ARM^® quad-core Cortex^®-A53 hard processor system (HPS) with a rich feature set of peripherals, including a system memory management unit, external memory controllers and high-speed communication interfaces. With Stratix 10 SoCs, Altera will extend its industry leadership position as the only vendor to offer high-end SoC FPGAs. This versatile computing platform offers exceptional adaptability, performance, power efficiency, system integration and design productivity for a broad range of high-performance applications. Architects can leverage Stratix 10 SoCs in high-performance systems to enable hardware virtualization, while adding management and monitoring capabilities, such as acceleration pre-processing, remote update and debug, configuration, and system performance monitoring.

Maximum Design Protection with Comprehensive Security Capabilities
Stratix 10 FPGAs and SoCs will feature the industry’s most comprehensive security capabilities in a high-performance FPGA. At its core is an innovative Secure Design Manager (SDM), which delivers sector-based authentication and encryption, multi-factor authentication and physically unclonable function (PUF) technology. Altera has partnered with Athena Group and IntrinsicID to deliver world-class encryption acceleration and PUF IP for Stratix 10 FPGAs and SoCs. This level of security makes Stratix 10 FPGAs and SoCs an ideal solution for use in military, cloud security and IoT infrastructure, where multi-layered security and partitioned IP protection are paramount.

Enpirion PowerSoCs Optimized for Stratix 10 FPGAs and SoCs
Stratix 10 FPGAs and SoCs are supported by Altera’s portfolio of Enpirion PowerSoC power solutions. Enpirion PowerSoCs are optimized to meet stringent performance and power requirements while offering high efficiency in the smallest footprint.

Industry’s Fastest Timing Closure for Multi-million LE Designs
Altera’s new Spectra-Q engine within the Quartus^® II software is designed to maximize the performance, power, and area saving benefits the HyperFlex architecture provides, while improving designer productivity and time-to-market for Stratix 10 FPGAs and SoCs. The Quartus II software extends Altera’s software leadership with new capabilities that will deliver up to 8X compile time improvements, versatile and fast-tracked design entry, drop-in IP integration, and support for OpenCL and other higher-level design flows. Additional information on the Spectra-Q engine is available at www.altera.com/spectraq.

Stratix 10 FPGA and SoC Technical Specifications:

• Up to 5.5 million logic elements in a monolithic die
• Heterogeneous 3D SiP integration combines FPGA fabric with high-speed transceivers
• Up to 144 transceivers deliver 4X serial bandwidth over the previous generation
• 64-bit quad-core ARM Cortex-A53 hard processor subsystem operating up to 1.5 GHz
• Hard floating point DSP enables single precision operations up to 10 TFLOPS throughput
• Secure Device Manager: Comprehensive high-performance FPGA security capabilities
• Industry-leading single-event upset (SEU) detection and scrubbing
• Footprint-compatible migration path from Arria® 10 FPGAs and SoCs
• Altera Enpirion power solutions offer maximum power efficiency and board area savings
• Intel 14 nm Tri-Gate process technology

Availability
Customers can get started on their Stratix 10 designs today using the Fast Forward Compile performance evaluation tools. Engineering samples of Stratix 10 FPGAs and SoCs will be available in the fall of 2015. Embedded software developers can leverage SoC virtual platforms from Mentor Graphics to accelerate Stratix 10 SoC embedded software development. For more information about Stratix 10 FPGA and SoC products, contact a local Altera sales representative or visit www.altera.com/stratix10.