Altera cores support PCI; inSilicon demos USB apps

Altera cores support PCI; inSilicon demos USB apps
By Michael Santarini, EE Times
June 12, 2000 (10:00 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000612S0012

Altera Corp. said its family of 32- and 64-bit, 33- and 66-MHz PCI MegaCore functions now supports CompactPCI and PCI 2.2 applications. That compliance lets Altera support embedded applications that require hot-swap capability to perform real-time system upgrades, reconfigurations and field replacements. Such applications include communications, computer telephony, real-time data acquisition, networking and industrial control.

The company offers fully parameterized PCI MegaCore functions supporting 64-bit Master/Target, 32-bit Master/Target, 64-bit Target Only and 32-bit Target Only apps.

The company said its PCI cores are capable of running at 66 Hz in Altera's Acex, Apex and Flex device families. It said the cores have been tested on Phoenix Technologies' Testbench, Hewlett-Packard's PCI Bus Analyzer and Altera's Flex 10KE PCI development board for optimal performance.

Altera also announced that PLD Applications is offering the HotSwap Now! CompactPCI board, an Altera Flex 10KE-based prototyping system that can be used in 5- and 3.3-volt, 32- and 64-bit, and 33- and 66-MHz CompactPCI environments. According to Altera, the board provides electrical, functional and timing compliance with CompactPCI and supports PLD Applications' 32- and 64-bit PCI Target and Master/Target cores, available through the Altera Megafunction Partners Program. The board offers field reprogramming of an Altera EPC2 configuration device, allowing OEMs to upgrade their applications via the Internet.

A connector provides support for in-system programming via Altera's ByteBlaster parallel port cable. Optional on-board SRAM is available in densities from 64 to 2,048 kbytes.

Altera's CompactPCI cores start at $4,995 for the 32-bit PCI Target MegaCore function. All PCI MegaCore functions include netlist, simulation vectors, documentation, and timing constraint files to guarantee timing compliance.

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IP vendor inSilicon Corp. ha s announced a working multivendor implementation of Universal Serial Bus (USB) 2.0. The company demonstrated the core at the USB 2.0 Developers Conference (Anaheim, Calif.). It said a Hewlett-Packard ScanJet scanner using an FPGA-based inSilicon USB 2.0 device core (UDC) transmitted a scanned image to a personal computer at bursts of 480 Mbits/second.

That rate, according to the company, is 40 times faster than the current USB 1.1 specification. The HP USB 2.0 capability is enabled in the scanner demonstration through an inSilicon device controller, operating in conjunction with a NEC Corp. USB 2.0 physical-layer test chip, communicating via a standard USB cable to an NEC host controller mounted on a PCI card in a PC.

USB is billed as enabling cost-effective, outside-the-box connectivity with hot-swap capability for industrial, consumer, embedded, PC and PC peripheral products. USB requires a host to manage and control bus traffic. USB 2.0 is a proposed specification designed to increase US B performance. The revision is fully compatible with USB 1.1. For more information on inSilicon's core visit www.in-silicon.com.